Methods and apparatus for packaging integrated circuit devices
View Patent ↗An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
1. An integrally packaged integrated circuit device comprising:
an integrated circuit die comprising:
a crystalline substrate having first and second generally planar surfaces and edge surfaces; and
an active surface formed on said first generally planar surface;
at least one chip scale packaging layer formed over said active surface;
at least one gap formed between said crystalline substrate and said at least one chip scale packaging layer; and
at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
2. An integrally packaged integrated circuit device according to claim 1 and wherein said at least one chip scale packaging layer is formed of a crystalline material.
3. An integrally packaged integrated circuit device according to claim 1 and wherein said crystalline substrate and said at least one chip scale packaging layer are both formed of silicon.
4. An integrally packaged integrated circuit device according to claim 1 and also comprising an insulation layer formed over said at least one chip scale packaging layer and directly underlying said at least one electrical contact.
5. An integrally packaged integrated circuit device according to claim 4 and wherein said insulation layer comprises at least one of a passivation layer and a dielectric layer.
6. An integrally packaged integrated circuit device according to claim 4 and wherein said insulation layer comprises at least one of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons and acrylates.
7. An integrally packaged integrated circuit device according to claim 1 and wherein said at least one chip scale packaging layer is formed of silicon.
8. An integrally packaged integrated circuit device according to claim 1 and wherein said gap is formed as a recess in said at least one packaging layer.
9. An integrally packaged integrated circuit device according to claim 1 and also including at least one gap formed in said crystalline substrate.
10. An integrally packaged integrated circuit device according to claim 1 and also including at least one gap formed in said crystalline substrate.
11. An integrally packaged integrated circuit device according to claim 1 and also including at least one gap formed in said crystalline substrate and at least one chip scale packaging layer formed underlying said crystalline substrate and sealing said gap formed in said crystalline substrate.