Nonvolatile memory device using semiconductor nanocrystals and method of forming same
View Patent ↗A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.
1. A floating gate for a field effect transistor, comprising:
a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
wherein said nanoparticles comprise a substantially uniform diameter, said nanoparticles comprising diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles,
wherein said nanoparticles comprise a substantially uniform center-to-center spacing between said nanoparticles, and
wherein said nanoparticles are arranged in a two-dimensional array.
2. The floating gate of claim 1 , wherein said spacing of said nanoparticles comprises a variance of no more than 20%.
3. The floating gate of claim 2 , wherein said spacing of said nanoparticles comprises a variance of no more than 15%.
4. The floating gate of claim 3 , wherein said spacing of said nanoparticles comprises a variance of no more than 10%.
5. The floating gate of claim 1 , wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of 10% to about 20%.
6. A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between said source region and said drain region;
an insulating layer of electrically insulating material disposed over said channel region;
a floating gate layer of electrically conducting material disposed over said insulating layer;
a layer of electrically insulating material disposed over said floating gate layer; and
a gate electrode overlying said layer of insulating material,
wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is one of templated and defined by a self-assembled material,
wherein said nanoparticles comprise a substantially uniform diameter, said nanoparticles comprising diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles,
wherein said nanoparticles comprise a substantially uniform center-to-center spacing between said nanoparticles, and
wherein said nanoparticle density is greater than 10 10 /cm 2 .
7. The field effect transistor of claim 6 , wherein said self assembly involves a block copolymer film.
8. The field effect transistor of claim 7 , wherein said block copolymer comprises a diblock copolymer including polystyrene (PS) and poly(methyl methacrylate) (PMMA).
9. The field effect transistor of claim 6 , wherein said nanoparticles comprise at least one of silicon, germanium, and silicon-germanium.
10. The field effect transistor of claim 6 , wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
11. The field effect transistor of claim 10 , wherein said hexagonal lattice comprises an average inter-nanoparticle distance between about 1 times and about 2 times an average nanoparticle diameter, and a standard deviation of inter-nanoparticle distance no greater than substantially 20% of the mean distance.
12. The field effect transistor of claim 6 , wherein said nanoparticles in said floating gate comprise a first distinct size and a second distinct size, each with diameter standard deviations being less than approximately 15% of a mean diameter of said nanoparticles.
13. The field effect transistor of claim 7 , wherein said block copolymer comprises a diblock copolymer comprising at least one of polystyrene (PS), poly(methyl methacrylate) (PMMA), polybutadiene-polybutylmethcrylate, polybutadiene-polydimethylsiloxane, polybutadiene-polymethylmethacrylate, polybutadiene-polyvinylpyridine, polyisoprene-polymethylmethacrylate, polyisoprene-polyvinylpyridine, polybutylacrylate-polymethylmethacrylate, polybutylacrylate-polyvinylpyridine, polyhexylacrylate-polyvinylpyridine, polyisobutylene-polybutylmethacrylate, polyisobutylene-polydimethoxysiloxane, polyisobutylene-polymethylmethacrylate, polyisobutylene-polyvinylpyridine, polybutylmethacrylate-polybutylacrylate, polybutylmethacrylate-polyvinylpyridine, polyethylene-polymethylmethacrylate, polymethylmathacrylate-polybutylacrylate, polymethylmethacrylate-polybutylmethacrylate, polystyrene-polybutadiene, polystyrene-polybutylacrylate, polystyrene-polybutylmethacrylate, polystyrene-polybutylstyrene, polystyrene-polydimethoxysiloxane, polystyrene-polyisoprene, polystyrene-polymethylmethacrylate, polystyrene-polyvinylpyridine, polyethylene-polyvinylpyridine, polyvinylpyridine-polymethylmethacrylate, polyethyleneoxide-polyisoprene, polyethyleneoxide-polybutadiene, polyethyleleoxide-polystyrene, and polyetheleneoxide-polymethylmethacrylate.
14. The field effect transistor of claim 6 , wherein said nanoparticles are arranged in one of a hexagonal lattice and a cubic lattice.
15. The field effect transistor of claim 7 , wherein said block copolymer comprises a diblock copolymer comprising a molecular weight within a range of about 5,000 kg/mol to about 250,000 kg/mol.
16. The field effect transistor of claim 7 , wherein a molecular weight of said block copolymer film is selected to determine dimensions of said nanoparticles.
17. The field effect transistor of claim 7 , wherein a molecular weight of said block copolymer film is selected to determine a diameter of said nanoparticles after said self-assembly and a spacing between adjacent ones of said nanoparticles.
18. The floating gate of claim 1 , wherein said self-assembled material uses a material which naturally forms a regular array.
19. A floating gate for a field effect transistor, comprising:
a plurality of discrete nanoparticles in which at least one of a size, spacing and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
wherein said nanoparticles comprise diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles, and
wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of about 10% to about 20%.
20. A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between said source region and said drain region;
an insulating layer of electrically insulating material disposed over said channel region;
a floating gate layer of electrically conducting material disposed over said insulating layer;
a layer of electrically insulating material disposed over said floating gate layer; and
a gate electrode overlying said layer of insulating material,
wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material, and
wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
21. A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between said source region and said drain region;
an insulating layer of electrically insulating material disposed over said channel region;
a floating gate layer of electrically conducting material disposed over said insulating layer;
a layer of electrically insulating material disposed over said floating gate layer; and
a gate electrode overlying said layer of insulating material,
wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice, and
wherein said hexagonal lattice comprises an average inter-nanoparticle distance between about 1 times and about 2 times an average nanoparticle diameter, and a standard deviation of inter-nanoparticle distance no greater than substantially 20% of the mean distance.
22. A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between said source region and said drain region;
an insulating layer of electrically insulating material disposed over said channel region;
a floating gate layer of electrically conducting material disposed over said insulating layer;
a layer of electrically insulating material disposed over said floating gate layer; and
a gate electrode overlying said layer of insulating material,
wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material, and
wherein said nanoparticles in said floating gate comprise a first distinct size and a second distinct size, each with diameter standard deviations being less than approximately 15% of a mean diameter of said nanoparticles.
23. A floating gate for a field effect transistor, comprising:
a plurality of discrete nanoparticles, wherein said nanoparticles have diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of mean diameter of the nanoparticles,
wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of no greater than about 20%, and
wherein said nanoparticles are arranged in a two-dimensional array.
24. A field effect transistor, comprising:
a floating gate, comprising:
a plurality of discrete nanoparticles, wherein said nanoparticles have diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of mean diameter of the nanoparticles,
wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of no greater than about 20%, and
wherein said nanoparticles are arranged in a two-dimensional array.
25. A floating gate for a field effect transistor, comprising:
a plurality of discrete nanoparticles,
wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
26. A field effect transistor, comprising:
a floating gate, comprising:
a plurality of discrete nanoparticles,
wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
27. The field effect transistor according to claim 10 , wherein said two-dimensional hexagonal lattice is imperfect, having defects in the form of grain boundaries.