Antifuse structure and a method of forming an antifuse structure
View Patent ↗The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, the first being a lower electrode that is disposed on an impurity region in a semiconductor substrate. A dielectric layer is disposed on the lower electrode, wherein the dielectric layer has a planar surface. A non-conductive hemispherical grain (HSG) layer is formed on the planar surface of the dielectric layer and an upper electrode is disposed on said non-conductive hemispherical grain (HSG) layer forming the antifuse.
1. An antifuse, comprising:
a lower electrode layer;
a dielectric layer disposed on said lower electrode layer;
a non-conductive hemispherical grain layer formed on said dielectric layer; and
an upper electrode disposed on said non-conductive hemispherical grain layer.
2. The antifuse of claim 1 , wherein said dielectric layer is disposed in physical communication with said non-conductive hemispherical grain layer and said lower electrode layer.
3. The antifuse of claim 1 , wherein said dielectric layer has at least one planar surface.
4. The antifuse of claim 1 , wherein said non-conductive hemispherical grain layer comprises amorphous Si.
5. The antifuse of claim 1 , wherein said non-conductive hemispherical grain layer comprises amorphous SiGe.
6. The antifuse of claim 1 , wherein said non-conductive hemispherical grain layer comprises amorphous carbon.
7. The antifuse of claim 6 , wherein said amorphous carbon of said non-conductive hemispherical grain layer is doped with at least one of hydrogen and fluorine.
8. The antifuse of claim 1 , wherein said non-conductive hemispherical grain layer is disposed between two layers of an adhesion-promoting material.
9. The antifuse of claim 1 , wherein said dielectric layer and said nonconductive hemispherical grain layer form a dielectric element.
10. The antifuse of claim 9 , wherein said dielectric element is about 5 Å to about 200 Å in thickness.
11. The antifuse of claim 1 , wherein said non-conductive hemispherical grain layer is about 100 Å to about 500 Å in thickness.
12. A method of forming an antifuse, comprising:
disposing a dielectric layer on a lower electrode layer;
forming a non-conductive hemispherical grain layer on said dielectric layer; and
disposing an upper electrode on said non-conductive hemispherical grain layer.
13. The method of claim 1 , wherein said dielectric layer is in physical communication with said non-conductive hemispherical grain layer and said lower electrode layer.
14. The method of claim 12 , wherein said dielectric layer has at least one planar surface.
15. The method of claim 12 , wherein said non-conductive hemispherical grain layer comprises amorphous Si.
16. The method of claim 12 , wherein said non-conductive hemispherical grain layer comprises amorphous SiGe.
17. The method of claim 12 , wherein said non-conductive hemispherical grain layer comprises amorphous carbon.
18. The method of claim 17 , wherein said amorphous carbon of said non-conductive hemispherical grain layer is doped with at least one of hydrogen and fluorine.
19. The method of claim 12 , wherein said non-conductive hemispherical grain layer is disposed between two layers of an adhesion-promoting material.
20. The method of claim 12 , wherein said dielectric layer and said nonconductive hemispherical grain layer form a dielectric element.
21. The method of claim 20 , wherein said dielectric element is about 5 Å to about 200 Å in thickness.
22. The method of claim 12 , wherein said non-conductive hemispherical grain layer is about 100 Å to about 500 Å in thickness.
23. The method of claim 12 , wherein said forming said non-conductive hemispherical grain layer includes vacuum annealing said non-conductive hemispherical grain layer.
24. The method of claim 12 , wherein said forming said non-conductive hemispherical grain layer includes use of a process selected from the group consisting of a vacuum anneal process, a low-pressure chemical vapor deposition process, and an in-situ annealing process.