IP Library Granted Patent US 7,968,859
Granted Patent B2
US 7,968,859 · App. 10/628,614 · Granted Jun 28, 2011

Wafer edge defect inspection using captured image analysis

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Quick Facts
Patent No.
US 7,968,859
App. No.
10/628,614
Granted
Jun 28, 2011
Kind
B2
Abstract

A wafer edge defect inspection method and apparatus for use in an integrated circuit fabrication system includes an image capturing device for capturing images of the edges of wafers, a database in which the images are stored and accessible for analysis and a computer for analyzing the images of one or more wafer edges to locate edge defects and for evaluating the performance of the fabrication system. The inspection and data storage are performed automatically. The database storage enables detailed analysis of many wafers and fabrication process steps.

Claims (72)

1. A method of inspecting a semiconductor wafer for defects using captured image analysis comprising:

positioning the wafer with an edge thereof relative to an image capturing device;

positioning the image capturing device at a desired angle relative to the edge of the wafer;

rotating the wafer;

scanning the edge of the rotating wafer with the image capturing device;

recording an image of a desired portion of the edge of the scanned wafer from the image capturing device into a database;

instructing a computer to analyze the recorded images of the scanned wafer;

identifying any defects in the analyzed recorded images; and

upon identifying any defects, recording defect information related to each defect;

wherein:

the scanning step further comprises:

scanning the edge of the wafer from a region interior of a top of the edge to a region exterior of a bottom of the edge.

2. A method of inspecting a semiconductor wafer for defects using captured image analysis comprising:

after a first process step:

positioning the wafer with an edge thereof relative to an image capturing device;

rotating the wafer;

scanning the edge of the rotating wafer with the image capturing device;

recording an image of the scanned wafer from the image capturing device into a database;

instructing a computer to analyze the recorded images of the scanned wafer;

identifying any defects in the analyzed recorded images; and

upon identifying any defects, recording defect information related to each defect;

after a second process step, repeating the aforementioned steps;

comparing the defect information recorded after the first process step to the defect information recorded after the second process step; and

identifying any new defects as added defects due to the second process step.

3. A method of inspecting a semiconductor wafer for defects using captured image analysis comprising:

after a first process step:

positioning the wafer with an edge thereof relative to an image capturing device;

rotating the wafer;

scanning the edge of the rotating wafer with the image capturing device;

recording an image of the scanned wafer from the image capturing device into a database;

instructing a computer to analyze the recorded images of the scanned wafer, identifying any defects in the analyzed recorded images; and

upon identifying any defects, recording defect information related to each defect;

after a second process step, repeating the aforementioned steps;

comparing the defect information recorded after the first process step to the defect information recorded after the second process step;

determining whether any defects identified after the first process step have been reduced after the second process step; and

identifying any such reduced defects as repaired defects.

4. A method of inspecting an edge of a semiconductor wafer for defects during fabrication of integrated circuit components on the semiconductor wafer within a fabrication system that includes a plurality of fabrication stations arranged in a processing order and within which a variety of process steps are performed on a plurality of wafers, comprising:

providing a plurality of inspection stations within the fabrication system corresponding to selected ones of the fabrication stations, each inspection station being located in a subsequent processing order to a corresponding one of the selected fabrication stations;

processing a wafer in a first fabrication station;

automatically inspecting an edge of the wafer in a first inspection station;

automatically recording a first set of defects in the edge of the wafer; processing the wafer in a second fabrication station;

automatically inspecting the edge of the wafer in a second inspection station;

automatically recording a second set of defects in the edge of the wafer; and

determining a difference between the first and second sets of defects.

5. A method as defined in claim 4 further comprising:

identifying process-induced edge defects from the determined difference between the first and second sets of defects.

6. A method of inspecting an edge of semiconductor wafers for defects during fabrication of integrated circuit components on the semiconductor wafers within a fabrication system that includes a plurality of fabrication stations arranged in a processing order and within which a variety of process steps are performed on a plurality of wafers, comprising:

providing a plurality of inspection stations within the fabrication system corresponding to selected ones of the fabrication stations, each inspection station being located in a subsequent processing order to a corresponding one of the selected fabrication stations;

processing the wafers in the fabrication stations;

inspecting the edge of the wafers in the inspection stations;

upon inspecting each wafer, recording an image of the edge of the wafer;

correlating each recorded image with the wafer from which it was taken and the process step after which it was taken;

selecting two recorded images from among a plurality of the recorded images by specifying the wafer from which both images were taken and the two process steps after which each selected image was taken;

determining any defects that were present on the edge of the specified wafer at times that the two selected recorded images were taken of the edge of the specified wafer by analyzing the two selected recorded images; and

determining whether any defects were added to the edge of the specified wafer between the times that the two selected recorded images were taken by comparing the determined defects from the analyzing of the two selected recorded images.

7. A wafer edge defect inspection system comprising:

an image capturing device next to which a wafer can be positioned, the image capturing device being oriented to view at least a portion of an edge of the wafer, the image capturing device automatically generating an image of the edge of the wafer;

a database connected to the image capturing device to receive the generated image of the edge of the wafer, the database automatically storing the received image for subsequent analysis; and

a computer connected to the database to retrieve the stored image upon instruction from a user to perform image analysis to locate any defects in the edge of the wafer;

wherein the image capturing device is a first image capturing device, the image generated thereby is a first image and the wafer edge defect inspection system is incorporated into a fabrication system having a plurality of fabrication stations for processing the wafer and forming integrated circuit components thereon, further comprising:

a second image capturing device next to which the wafer can be positioned, the second image capturing device being oriented to view at least the portion of the edge of the wafer, the second image capturing device automatically generating a second image of the edge of the wafer and being connected to the database to supply the second image to the database;

and wherein:

the database automatically stores the second image for subsequent analysis by the computer;

the first image capturing device is incorporated into the fabrication system to receive the wafer after a first fabrication station performs a first process step on the wafer and the first image capturing device generates the first image of the edge of the wafer after the first process step;

the second image capturing device is incorporated into the fabrication system to receive the wafer after a second fabrication station performs a second process step on the-wafer and the second image capturing device generates the second image of the edge of the wafer after the second process step; and

the computer retrieves the stored first and second images upon instruction from the user to compare and analyze the first and second images together.

8. A wafer edge defect inspection system as defined in claim 7 , wherein:

the computer compares and analyzes the first and second images together upon instruction from the user to determine whether any defects have been added to the edge of the wafer between times that the first and second images thereof are generated.

9. A wafer edge defect inspection system as defined in claim 7 , wherein:

the computer compares and analyzes the first and second images together upon instruction from the user to determine whether any defects have been repaired on the edge of the wafer between times that the first and second images thereof are generated.

10. A wafer edge defect inspection system as defined in claim 7 incorporated into a fabrication system having a plurality of fabrication stations within which the wafer is subjected to process steps to form integrated circuit components thereon, and wherein:

at least a portion of the located defects are caused by at least one of the process steps to which the wafer is subjected before the image capturing device automatically generates the image of the edge of the wafer.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2003
From: YOUNG, ROGER Y.B.; KNOCH, JOHN A.; MCNICHOLS, JASON W.
To: LSI LOGIC CORPORATION
Reel/Frame 014338/0798 →