Multilayered cap barrier in microelectronic interconnect structures
View Patent ↗Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.
1. An interconnect structure comprising
at least one conducting metal feature on a substrate, said substrate further comprising an interlayer dielectric layer surrounding said conducting metal feature, a multilayered dielectric diffusion barrier layer that is a barrier to metal diffusion and is comprised of at least two sublayers where at least one sublayer is an air barrier sublayer which prohibits air permeation and at least another sublayer is a low-k sublayer that is comprised of Si v N w C x O y H z where 0.1≦v≦0.8, 0≦w≦0.8, 0.05x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8, and v+w+x+y+z=1, and
an interlayer dielectric that is comprised of a line level dielectric and a via level dielectric.
2. The structure of claim 1 , wherein the multilayered dielectric diffusion barrier layer has a composite dielectric constant less than 4.0.
3. The structure of claim 1 , wherein the air barrier sublayer is a dielectric comprised of a silicon nitride, silicon carbonitride, silicon oxynitride, silicon dioxide, silicon carbide, or fluorinated glass.
4. The structure of claim 1 , wherein the air barrier sublayer is a dielectric that has a composition of Si v N w C x O y H z where 0.1≦v≦0.8, 0≦w≦0.8, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8, and v+w+x+y+z=1.
5. The structure of claim 1 , wherein the low-k sublayer contains porosity.
6. The structure of claim 5 , wherein the porosity has a closed cell morphology.
7. The structure of claim 1 , wherein the multilayered dielectric diffusion barrier layer is a bilayer with the low-k sublayer atop the air barrier sublayer.
8. The structure of claim 1 , wherein the multilayered dielectric diffusion barrier layer is a bilayer where the air barrier sublayer atop the low-k sublayer.
9. The structure of claim 1 , wherein the multilayered dielectric diffusion barrier layer is a trilayer with the air barrier sublayer placed between two low-k sublayers.
10. The structure of claim 1 , wherein the interconnect structure further comprises at least one low dielectric constant material, said low dielectric constant material is comprised of at least one of polysiloxanes, polysilsesquioxanes, polyarylenes, poly(arylene ethers), or a dielectric that is generated by a vapor deposition approach producing a film having the composition Si v N w C x O y H z where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.8, 0.05≦z≦0.8 for v+w+x+y+z=1.
11. The structure of claim 10 , wherein the low dielectric constant material is porous.
12. The structure of claim 1 , wherein the via level dielectric is comprised of at least one low dielectric constant material and the multilayered dielectric diffusion barrier layer.
13. The structure of claim 1 , wherein the via level dielectric is comprised solely of the multilayered dielectric diffusion barrier layer.
14. The structure of claim 1 , wherein the interlayer dielectric is comprised of a line level dielectric of one composition and a via level dielectric having two distinct compositions where the dielectric directly under conducting metal features are of one composition and dielectrics not directly under conducting metal features have the identical composition to the line level dielectric.
15. The structure of claim 1 , wherein the conducting metal lines comprise a metal at the top surface that reduces the electromigration characteristics of the interconnect structure.
16. The structure of claim 1 , wherein the conducting metal lines comprise a moiety at the top surface that reduces the propensity of the metal lines to oxidize, said moiety is one of benzotriazoles, amines, amides, imides, thioesters, thioethers, ureas, urethanes, nitriles, isocyanates, thiols, sulfones, phosphines, phosphine oxides, phosphonimides, pyridines, imidazoles, imides, oxazoles, benzoxazoles, thiazoles, pyrazoles, triazoles, thiophenes, oxadiazoles, thiazines, thiazoles, quionoxalines, benzimidazoles, oxindoles, or indolines.
17. The structure of claim 1 , wherein the line level dielectric comprises a hardmask dielectric that differs in composition from the line level dielectric.
18. The structure of claim 17 , wherein the hardmask dielectric comprises a polysiloxane, polysilsesquioxane, or any CVD deposited dielectric having the composition Si v N w C x O y H z where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.8, 0.05≦z≦0.8 for v+w+x+y+z=1.
19. The structure of claim 1 , wherein the line level dielectric and via level dielectric is separated by a dielectric etch stop layer.
20. The structure of claim 19 , wherein the dielectric etch stop layer comprises a polysiloxane, polysilsesquioxane, or any CVD deposited dielectric having a composition comprised of Si v N w C x O y H z where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.8, 0.05≦z≦0.8 for v+w+x+y+z=1.
21. The structure of claim 1 , wherein at least one adhesion promoter is present between the multilayered dielectric diffusion barrier layer and dielectric layers above and/or below the multilayered dielectric diffusion barrier layer.
22. The structure of claim 1 , wherein at least one adhesion promoter is present between the sublayers of the multilayered dielectric diffusion barrier layer.