IP Library Granted Patent US 7,045,393
Granted Patent B2
US 7,045,393 · App. 10/668,492 · Granted May 16, 2006

Method for manufacturing circuit devices

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Quick Facts
Patent No.
US 7,045,393
App. No.
10/668,492
Granted
May 16, 2006
Kind
B2
Abstract

Conventionally, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate ( 10 ) in which a thin first conductive film ( 11 ) and a thick second conductive film ( 12 ) have been laminated via a third conductive film ( 13 ) is used. In a step for forming a conductive wiring layer ( 11 A) by etching the first conductive film ( 11 ), etching depth can be controlled by stopping etching at the third conductive film ( 13 ). Accordingly, forming the first conductive film ( 11 ) to be thin makes it possible to form the conductive wiring layer ( 11 A) into a fine pattern.

Claims (27)

1. A method for manufacturing circuit devices comprising:

preparing a laminated plate by laminating a first conductive film and a second conductive film via a third conductive film;

forming a conductive wiring layer by etching said first conductive film into a pattern;

removing said third conductive film by use of said conductive wiring layer as a mask;

covering front-surface portions of the second conductive film exposed by removing said third conductive film, said conductive wiring layer, and end faces of the third conductive film with an insulating layer;

partially exposing said conductive wiring layer by removing a part of said insulating layer;

fixedly fitting semiconductor elements onto said insulating layer and electrically connecting said semiconductor elements with said conductive wiring layer;

covering said semiconductor elements with a sealing resin layer; and

removing said second conductive film to expose said third conductive film on the rear surface.

2. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in a step of etching said first conductive film, said conductive wiring layer is formed by performing etching up to said third conductive film.

3. The method for manufacturing circuit devices as set forth in claim 2 , wherein, in the step of etching said first conductive film, said first conductive film is etched with a solution.

4. The method for manufacturing circuit devices as set forth in claim 2 or 3 , wherein, in the step of etching said first conductive film, a solution containing ferric chloride or cupric chloride is used to etch the first conductive film.

5. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in a step of removing said third conductive film, said third conductive film is removed by electrolytic peeling.

6. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in a step of removing said third conductive film, said third conductive film is removed by using a solution to etch said third conductive film.

7. The method for manufacturing circuit devices as set forth in claim 6 , wherein said solution is an iodine-based solution.

8. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in a step of removing said second conductive film, said second conductive film is entirely etched.

9. The method for manufacturing circuit devices as set forth in claim 1 , wherein said second conductive film is thicker than said first conductive film.

10. The method for manufacturing circuit devices as set forth in claim 1 , wherein said insulating layer can be a thermoplastic resin, a thermosetting resin, or a photosensitive resin.

11. The method for manufacturing circuit devices as set forth in claim 1 , wherein said first conductive film and said second conductive film are metals made of copper as a main material, and said third conductive film is a metal made of silver as a main material.

12. The method for manufacturing circuit devices as set forth in claim 1 , wherein said laminated plate is manufactured by laminating said third conductive film and said first conductive film by electroplating while using said second conductive film as a base.

13. The method for manufacturing circuit devices as set forth in claim 1 , wherein said laminated plate is formed by rolling.

14. The method for manufacturing circuit devices as set forth in claim 1 , wherein electronic components, other than semiconductor components, are electrically connected to said conductive wiring layer.

15. The method for manufacturing circuit devices as set forth in claim 1 , wherein said insulating layer is formed by vacuum press or vacuum lamination.

16. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in a step of partially exposing said conductive wiring layer, said insulating layer is partially removed by laser processing.

17. The method for manufacturing circuit devices as set forth in claim 1 , wherein, in the step of partially exposing said conductive wiring layer, said insulating layer is partially removed by a lithographic method.

18. The method for manufacturing circuit devices as set forth in claim 1 , wherein a plated layer is formed on the exposed parts of said conductive wiring layer by electrolytic plating in which the second conductive layer is used as an electrode.

19. The method for manufacturing circuit devices as set forth in claim 1 , further comprising forming external electrodes at particular positions of said third conductive film.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2014
From: KANTO SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033713/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033670/0750 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2004
From: IGARASHI, YUSUKE; SAKAMOTO, NORIAKI
To: SANYO ELECTRIC CO., LTD.; KANTO SANYO SEMICONDUCTORS CO., LTD.
Reel/Frame 014884/0471 →