Block symmetrization in a field programmable gate array
View Patent ↗A architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT 3 s , a LUT 2 , and a DFF. Each of the LUT 3 s have three inputs and one output. Each of the LUT 2 s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUTs are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.
1. A logic cluster in a logic block of a field programmable gate array, comprising:
a plurality of look-up tables wherein each of said plurality of look-up tables has a plurality of inputs and a single output;
a D-type flip-flop having an input and an output;
a first plurality of NMOS transistors wherein a source of each of said first plurality is connected to an output of different ones of said plurality of look-up tables and said drain is connected to an input of said D-type flip-flop and a gate controlled by a first signal;
a second plurality of NMOS transistors wherein a source of each of said first plurality is connected to an output of different ones of said plurality of look-up tables and said drain is connected to an output of said D-type flip-flop and a gate controlled by a complement of said first signal controlling said gate of the one of said first plurality of NMOS transistors having a source connected to said output of different one of said plurality of look-up tables;
a third plurality of NMOS transistors wherein each of said third plurality of NMOS transistors has a source connected said drain of one of said second plurality of NMOS transistors, a gate connected to said output of said D-type output device and gates of other ones of said third plurality of transistors, and a gate controlled by said first signal controlling said one of said first plurality of NMOS transistors connected to said ones of said second plurality of transistors connected to said source;
a plurality of inverters wherein each of said inverters is connected to a drain of one of said second plurality of transistors and said source of said one of said third plurality of transistors connected to said drain of said one of second plurality of transistors;
a fourth plurality of NMOS transistors wherein each of said plurality of fourth NMOS transistors has a source connected to one of said plurality of invertors, a drain connected to one of a plurality of output nodes, and a gate controlled by a second signal; and
a fifth plurality of NMOS transistors wherein each of said plurality of fifth NMOS transistors has a source connected to one of said plurality of invertors, a drain connected to one of a plurality of output nodes wherein said one of said plurality of output nodes is connected to a drain of one of said fourth plurality of NMOS transistors connected to another one of said plurality of transistors, and a gate controlled by an inverse of said second signal controlling said one of said fourth plurality of NMOS transistors.