Polycarbosilane buried etch stops in interconnect structures
View Patent ↗Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition Si v N w C x O y H z , where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
1. An interconnect structure comprising:
a buried etch stop layer comprised of a polymeric material having a composition Si v N w C x O y H z , where 0.05≦v≦0.8, w=0, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1;
a via level interlayer dielectric that is directly below said buried etch stop layer;
a line level interlayer dielectric that is directly above said buried etch stop layer; and
conducting metal features that traverse through said via level interlayer dielectric, said line level interlayer dielectric, and said buried etch stop layer.
2. The interconnect structure of claim 1 wherein said polymeric material is selected from a group consisting of: polysilanes, polycarbosilanes, polysilylenemethylenes, polysilacarbosilanes, and polysiloxazanes.
3. The interconnect structure of claim 1 wherein said buried etch stop layer comprises polyallylhydridocarbosilane or polycarbomethylsilane.
4. The interconnect structure of claim 1 wherein said buried etch stop layer has a dielectric constant ranging from about 1.4 and about 2.2.
5. The interconnect structure of claim 1 wherein said buried etch stop layer has a dielectric constant ranging from about 2.2 to about 3.8.
6. The interconnect structure of claim 1 wherein said buried etch stop layer is porous.
7. The interconnect structure of claim 1 wherein adhesion promoters are positioned on an interface of said buried etch stop layer.
8. The interconnect structure of claim 1 wherein said buried etch stop layer and said via level interlayer dielectric have an identical pattern.
9. The interconnect structure of claim 1 wherein said buried etch stop layer is permeable to low molecular weight volatile products.
10. The interconnect structure of claim 1 wherein said buried etch stop layer is thermally stable to temperatures greater than about 350° C.
11. The interconnect structure of claim 1 wherein said via level interlayer dielectric and said line level interlayer dielectric are identical materials.
12. The interconnect structure of claim 1 wherein said via level interlayer dielectric and said line level interlayer dielectric are different materials.
13. The interconnect structure of claim 1 wherein said buried etch stop layer has a thickness of about 5.0 nanometers to about 50.0 nanometers.
14. The interconnect structure of claim 1 wherein said via level interlayer dielectric, said line level interlayer dielectric or a combination of said via level interlayer dielectric and said line level interlayer dielectric each have a thickness ranging from about 30 nanometers to about 500 nanometers.
15. The interconnect structure of claim 1 wherein said conducting metal features are selected from the group consisting of: copper, aluminum, gold, silver, and alloys thereof.
16. The interconnect structure of claim 15 wherein said conducting metal features have a lining comprising a metal containing barrier layer, wherein said metal containing barrier layer is selected from a group consisting of: tantaulum, tungsten, ruthenium, cobalt, and titanium.