Neo-wafer device and method
View Patent ↗A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. A substrate is provided and includes a dielectric layer with conductive pads for the receiving of one or more integrated circuit die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the conductive pads, creating a neo-wafer from which stackable neo-layers with known good die can be singulated.
1. A neo-wafer comprising:
at least one IC chip with an active surface and an inactive surface, said active surface having at least one I/O pad,
an isolation layer, said isolation layer having at least one conductive pad formed thereon,
said at least one IC chip disposed upon said isolation layer, said active surface oriented toward said isolation layer,
an electrical interconnection between said conductive pad and said I/O pad, an under-fill material disposed in the volume between said active surface and said isolation layer,
said at least one IC chip encapsulated in an encapsulant, and,
said at least one conductive pad exposed upon the surface of and electrically accessible through said isolation layer.
2. The neo-wafer of claim 1 wherein said isolation layer is comprised of a polyimide material.
3. The neo-wafer of claim 1 wherein said at least one conductive pad is exposed by means of a back-thinning process.
4. The neo-wafer of claim 1 wherein said at least one conductive pad is exposed by means of a mechanical grinding process.
5. The neo-wafer of claim 1 wherein said at least one conductive pad is exposed by means of a chemical etching process.