Chip carrier substrate with a land grid array and external bond terminals

1. A carrier for a semiconductor die comprising:

a substrate having a cavity formed in said substrate, said cavity having a bottom and sidewalls, said sidewalls having a stepped tier;

a plurality of electrically conductive contacts on an underside of said substrate;

a plurality of electrically conductive tabs disposed on said stepped tier;

a plurality of electrically conductive external bond terminals disposed on an edge of said substrate; and

a plurality of electrically conductive paths formed in said substrate and electrically coupled between said electrically conductive tabs, said electrically conductive contacts, and said electrically conductive external bond terminals.

2. A carrier for a semiconductor die as in claim 1 , wherein said substrate is formed from a multilayer of ceramic substrates.

3. A carrier for a semiconductor die as in claim 1 , wherein said substrate is formed from laminates of organic dielectrics.

4. A carrier for a semiconductor die as in claim 1 , wherein said substrate is formed from deposited thin film layers.

5. A carrier for a semiconductor die as in claim 1 further including a sealing lid disposed on said substrate and covering said cavity.

6. A carrier for a semiconductor die as in claim 1 further including a plurality of wires electrically coupled between the semiconductor die and the plurality of electrically conductive tabs.

7. A carrier for a semiconductor die as in claim 1 wherein said plurality of electrically conductive external bond terminals disposed on an edge of said substrate are disposed on a ledge in a recess formed in said edge of said substrate.

8. A carrier for a semiconductor die as in claim 1 wherein said plurality of electrically conductive paths are formed from conductive vias and conductive lines in said substrate.

9. A carrier for a semiconductor die as in claim 1 wherein said sidewalls have a plurality of stepped tiers and said plurality of electrically conductive tabs are disposed on said plurality of stepped tiers.

10. A carrier for a semiconductor die comprising:

a substrate having an upper surface and a lower surface;

a plurality of electrically conductive surface contacts disposed on said upper surface of said substrate;

a plurality of electrically conductive contacts on an underside of said substrate;

a plurality of electrically conductive external bond terminals disposed on an edge of said substrate; and

a plurality of electrically conductive paths formed in said substrate and electrically coupled between said electrically conductive surface contacts, said electrically conductive contacts, and said electrically conductive external bond terminals.

11. A carrier for a semiconductor die as in claim 10 , wherein said substrate is formed from a multilayer of ceramic substrates.

12. A carrier for a semiconductor die as in claim 10 , wherein said substrate is formed from laminates of organic dielectrics.

13. A carrier for a semiconductor die as in claim 10 , wherein said substrate is formed from deposited thin film layers.

14. A carrier for a semiconductor die as in claim 10 further including a cover disposed on said substrate and covering the semiconductor die.

15. A carrier for a semiconductor die as in claim 10 wherein the semiconductor die has a plurality of semiconductor die contacts electrically connected to said plurality of electrically conductive surface contacts.

16. A carrier for a semiconductor die as in claim 10 wherein said plurality of electrically conductive external bond terminals disposed on an edge of said substrate are disposed on a ledge in a recess formed in said edge of said substrate.

17. A carrier for a semiconductor die as in claim 10 wherein said plurality of electrically conductive paths are formed from conductive vias and conductive lines in said substrate.