Semiconductor device, method for manufacturing same and thin plate interconnect line member
View Patent ↗The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410 a and 410 b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.
1. A semiconductor device, comprising:
an insulating resin layer; and
a semiconductor chip mounted on said insulating layer;
wherein said insulating resin layer includes a patterned interconnect line embedded therein,
wherein said insulating resin layer has a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02, and
wherein surface roughness Ra of said patterned interconnect line is equal to or less than 1 μm.
2. The semiconductor device according to claim 1 , wherein water absorption of said insulating resin layer is equal to or less than 0.1%.
3. The semiconductor device according to claim 1 , wherein said insulating resin layer includes a patterned interconnect line having a multi-layer structure embedded therein.
4. The semiconductor device according to claim 1 , wherein said insulating resin layer contains liquid crystal polymer, epoxy resin or BT resin.
5. The semiconductor device according to claim 1 , wherein said semiconductor chip is flip-chip mounted on said insulating layer.
6. A thin plate interconnect line member having a semiconductor chip-mounting surface and an interconnect line substrate-coupling surface opposite to said chip-mounting surface, comprising:
an insulating resin layer; and
a patterned interconnect line being embedded within said insulating resin layer,
wherein at least a part of said patterned interconnect line is exposed on said interconnect line substrate-coupling surface,
wherein said insulating resin layer has a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02, and
wherein the surface roughness Ra of said patterned interconnect line is equal to or less than 1 μm.
7. The thin plate interconnect line member according to claim 6 , wherein water absorption of said insulating resin layer is equal to or less than 0.1%.
8. The thin plate interconnect line member according to claim 6 , wherein a patterned interconnect line having a multi-layer structure is embedded in said insulating resin layer.
9. The thin plate interconnect line member according to claim 6 , wherein said insulating resin layer contains liquid crystal polymer, epoxy resin or BT resin.