IP Library Granted Patent US 7,148,146
Granted Patent B1
US 7,148,146 · App. 10/733,034 · Granted Dec 12, 2006

Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination

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Quick Facts
Patent No.
US 7,148,146
App. No.
10/733,034
Granted
Dec 12, 2006
Kind
B1
Abstract

A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Claims (15)

1. A method of fabricating a capacitor on a substrate comprising the steps of:

performing capacitor foundation formation on the substrate;

depositing polish stop layer material on the capacitor foundation and the substrate;

etching a first capacitor electrode region on the capacitor foundation formation and a transistor gate region on the substrate;

depositing a first conductive material in the etched first capacitor electrode region and the transistor gate region;

performing chemical mechanical polishing on the deposited first conductive material to yield a gate electrode and a first capacitor electrode;

depositing a dielectric material over the gate electrode and the first capacitor electrode;

etching a second capacitor electrode region in the dielectric material over the first capacitor electrode and into the first capacitor electrode material;

forming a capacitor dielectric layer over the first capacitor electrode;

depositing a second conductive material in the etched second capacitor electrode region; and

performing chemical mechanical polishing on the deposited second conductive material to yield a second capacitor electrode.

2. The method of claim 1 , wherein the step of depositing polish stop layer material on the capacitor foundation substrate includes depositing polish stop layer material comprising an oxide.

3. The method of claim 1 , wherein the step of depositing polish stop layer material on the capacitor foundation substrate includes depositing polish stop layer material comprising a nitride.

4. The method of claim 1 , wherein the steps of performing chemical mechanical polishing on the deposited first conductive material to yield a first capacitor electrode yields a first electrode in the form of a plate, and performing chemical mechanical polishing on the deposited second conductive material to yield a second capacitor electrode yields a second electrode in the form of a plate.

5. The method of claim 1 , wherein the steps of performing chemical mechanical polishing on the deposited first conductive material to yield a first capacitor electrode yields a first substantially cylindrical electrode and performing chemical mechanical polishing on the deposited second conductive material to yield a second capacitor electrode yields a second substantially cylindrical electrode.

Assignments (9)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →