IP Library Granted Patent US 6,972,242
Granted Patent B2
US 6,972,242 · App. 10/741,498 · Granted Dec 6, 2005

Methods to fabricate semiconductor devices

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Quick Facts
Patent No.
US 6,972,242
App. No.
10/741,498
Granted
Dec 6, 2005
Kind
B2
Abstract

Semiconductor device fabrication methods are disclosed. According to one example, a method includes forming a pad oxide layer and a nitride layer sequentially on a silicon substrate, and forming a photoresist pattern for trench formation on the nitride layer; etching the nitride layer and the pad oxide layer using the photoresist pattern as a mask while etching the silicon substrate to form a trench using the nitride layer as an etch stopper; filling the trench by depositing an oxide layer for trench gap filling on entire surface of the silicon substrate; and performing planarization which makes the gap filling oxide exist only in the trench.

Claims (11)

1. A fabrication method of a semiconductor device comprising:

forming a pad oxide layer and a nitride layer sequentially on a silicon substrate, and forming a photoresist pattern for trench formation on the nitride layer;

etching the nitride layer and the pad oxide layer using the photoresist pattern as a mask while etching the silicon substrate to form a trench using the nitride layer as an etch stopper;

filling the trench by depositing an oxide layer for trench gap filling on entire surface of the silicon substrate; and

performing planarization which makes the gap filling oxide exist only in the trench;

wherein thickness of the photoresist layer is determined to make the photoresist layer be removed simultaneously by etching of the nitride layer the pad oxide layer, and the silicon substrate.

2. A fabrication method as defined by claim 1 , wherein the planarization of the gap filling oxide is performed by polishing the gap filling oxide by chemical mechanical polishing using the nitride layer as a buffer layer after filling up the trench with the gap filling oxide.

3. A fabrication method as defined by claim 1 , wherein the planarization of the gap filling oxide is performed by etch-back process.

4. A fabrication method as defined by claim 1 , wherein thickness of the photoresist which remains on the nitride layer before etching of the silicon substrate is 1000 Å–3000 Å if depth of the trench to be formed is 4000 Å–6000 Å.

5. A fabrication method as defined by claim 1 , further comprising over-etching the nitride layer at the etch stop point in which the photoresist pattern is completely etched after the formation of the trench.

6. A fabrication method as defined by claim 5 , further comprising forming a thermal oxide layer on inner wall of the trench by thermal oxidation process between the over-etching and the trench filling.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2020
From: COLUMBA TECHNOLOGIES, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052845/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
MERGER Recorded May 31, 2005
From: ANAM SEMICONDUCTOR INC.; ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATION
Reel/Frame 016593/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2004
From: LEE, DATE-GUN
To: ANAM SEMICONDUCTOR, INC.
Reel/Frame 014883/0375 →