IP Library Granted Patent US 7,226,838
Granted Patent B2
US 7,226,838 · App. 10/745,854 · Granted Jun 5, 2007

Methods for fabricating a semiconductor device

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Quick Facts
Patent No.
US 7,226,838
App. No.
10/745,854
Granted
Jun 5, 2007
Kind
B2
Abstract

Methods of fabricating a semiconductor device is disclosed. An illustrated method comprises: providing a substrate including an active region and a non-active region; forming a first gate electrode including a dielectric layer pattern, a first conducting layer pattern, and an insulating layer pattern; growing a thermal oxide layer on the substrate and the first gate electrode; forming a nitride layer over the substrate and the thermal oxide layer; and removing the nitride layer and the thermal oxide layer using an etch back process to form spacers on sidewalls of the first gate electrode. By including the thermal oxide layer, the spacers ensure insulation capability.

Claims (10)

1. A method for fabricating a semiconductor device comprising:

providing a semiconductor substrate;

forming a first gate electrode including a dielectric layer pattern, a first conducting layer pattern, and an insulating nitride layer pattern, the first gate electrode functioning as a flash memory, wherein the first conductive layer pattern consists of conductive material and the insulating nitride layer pattern is formed in contact with the first conducting layer pattern;

growing a thermal oxide layer on the semiconductor substrate, on sidewalls of the dielectric layer pattern and on sidewalls of the first conducting layer pattern up to a height of the first conducting layer such that the thermal oxide layer is not grown above the first conducting layer and is not grown on the sidewalls of the insulating nitride layer pattern;

forming a nitride layer on the thermal oxide layer and on the insulating nitride layer pattern;

partially removing the nitride layer and the thermal oxide layer to form spacers on sidewalls of the first gate electrode, the spacers comprising the nitride layer pattern and the thermal oxide layer pattern;

forming a second oxide layer on the semiconductor substrate but not on the first gate electrode or the spacers; and

forming a second conducting layer over the second oxide layer, the first gate electrode, and the spacers.

2. The method as defined by claim 1 , further comprising removing a residual insulating layer from the formation of the first gate electrode from the substrate.

3. The method as defined by claim 1 , wherein the thermal oxide layer is removed by an etch-back process.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2004
From: KIM, SEOK SU
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014894/0463 →