Method for packaging a multi-chip module of a semiconductor device
View Patent ↗A method for packaging a multi-chip module includes the steps of: connecting connection terminals of a tape of an anisotropic conductive adhesive film, on which a circuit is patterned to bond pads of the chip by applying an adhesive on the tape, applying an adhesive on an upper surface of the chip, folding the tape and attaching the folded tape to the upper surface of the chip and forming a plurality of ball terminals on a lower surface of the tape, the ball terminals being electrically connected to the connection terminals of the tape. An individual chip scale package may be manufactured by repeating the above steps.
1. A method for packaging a multi-chip module, comprising the steps of:
(a) connecting connection terminals of a tape of an anisotropic conductive adhesive film, on which a circuit is patterned to bond pads of a chip by applying a first anisotropic conductive adhesive on the tape and using a first C4 process;
(b) applying an adhesive on an upper surface of the chip, folding the tape and attaching the folded tape to the upper surface of the chip;
(c) forming a plurality of ball terminals on a lower surface of the tape, the ball terminals being electrically connected to the connection terminals of the tape;
(d) manufacturing a plurality of individual chip scale packages by repeating the steps (a) to (c); and
(e) laminating the individual chip scale packages, wherein the ball terminals of an upper individual chip scale package are electrically connected to the circuit on an outer surface of the tape which covers a lower individual chip scale package.
2. The method of claim 1 , further comprising the step of mounting the ball terminals of a lowest of the individual chip scale packages on a patterned circuit.
3. The method of claim 1 , wherein, in the step (b), the adhesive comprises a second anisotropic conductive adhesive.
4. The method of claim 1 , further comprising the step of providing an uppermost chip scale package on top of the laminated chip scale packages of step (e), wherein the tape covers only a lower surface of the uppermost individual chip scale package.
5. The method of claim 4 , wherein the step of providing an uppermost chip scale package comprises connecting connection terminals of a further tape of a further anisotropic conductive adhesive film on which a further circuit is patterned to bond pads of a further chip by applying a second adhesive on the tape, and forming a further plurality at ball terminals on a lower surface of the further tape, the further plurality of ball terminals being electrically connected to the connection terminals of the further tape.
6. The method of claim 5 , wherein the second adhesive comprises a third anisotropic conductive adhesive.
7. The method of claim 5 , wherein the step of connecting the connection terminals of the further tape uses a second C4 process.
8. The method of claim 1 , comprising the step of patterning the circuit on the tape.
9. The method of claim 1 , wherein, in the step (b), the adhesive comprises a thermal conductive adhesive.
10. The method of claim 2 , wherein the patterned circuit comprises a printed circuit board.