Radiation tolerant SRAM bit

1. In an integrated circuit, a radiation tolerant static random access memory device comprising:

a first inverter having an input and an output;

a second inverter having an input and an output, said output of said first inverter coupled to said input of said second inverter and said output of said second inverter coupled to said input of said first inverter;

a resistor coupled between said first and second inverter;

a pass transistor having a gate coupled to one of said first inverter output and said second inverter output, wherein;

an RC time constant of the static random access memory device exceeds a selected recovery time of the static random access memory device.

2. A radiation tolerant static random access memory device according to claim 1 , wherein:

the selected recovery time is long enough to negate the effect of a high-energy particle impact on the static random access memory device.

3. A radiation tolerant static random access memory device according to claim 1 further comprising:

a first write transistor coupled to said output of said first inverter and having a gate coupled to a source of write-control signals; and

a second write transistor coupled to said output of said second inverter and having a gate coupled to said source of write-control signals.

4. In an integrated circuit, a radiation tolerant static random access memory device comprising:

a first inverter having an input and an output;

a second inverter having an input and an output;

a first resistor coupled between said output of said first inverter and said input of said second inverter;

a second resistor coupled between said output of said second inverter and said input of said first inverter;

a first write transistor coupled to said output of said first inverter and having a gate coupled to a source of write-control signals;

a second write transistor coupled to said output of said second inverter and having a gate coupled to said source of write-control signals; and

a pass transistor having a gate coupled to said output of one of said first and second inverters.

5. A radiation tolerant static random access memory device according to claim 4 wherein said first and second inverters comprise a plurality of pass transistors.

6. In an integrated circuit, a method of producing a radiation tolerant static random access memory device comprising:

providing a first inverter having an input and an output;

coupling a second inverter having an input and an output to said output of said first inverter to said input of said second inverter and coupling said output of said second inverter to said input of said first inverter;

coupling a resistor between said first and second inverter; and

coupling a pass transistor gate to one of said first inverter output and said second inverter output;

coupling a first write transistor to said output of said first inverter and coupling a gate to a source of write-control signals; and

coupling a second write transistor to said output of said second inverter and coupling a gate to said source of write-control signals.

7. In an integrated circuit, a method of producing a radiation tolerant static random access memory device comprising:

providing a first inverter having an input and an output;

providing a second inverter having an input and an output;

coupling a first resistor between said output of said first inverter and said input of said second inverter;

coupling a second resistor between said output of said second inverter and said input of said first inverter;

coupling a first write transistor coupled to said output of said first inverter and coupling a gate of said first write transistor to a source of write-control signals;

coupling a second write transistor coupled to said output of said second inverter and coupling a gate of said second write transistor to said source of write-control signals; and

coupling a pass transistor having a gate to one of said first inverter output and said second inverter output.

8. A method of producing a radiation tolerant static random access memory device according to claim 7 wherein said first and second inverters comprise a plurality of pass transistors.

9. In a field programmable gate array circuit, a method of increasing radiation tolerance in a static random access memory device comprising:

providing a static random access memory device;

increasing the time constant for a write time of static random access memory device in order to make the static random access memory device more radiation tolerant;

wherein increasing the time constant comprises adding a resistor of approximately 4 mega ohms.

10. The method of increasing radiation tolerance in a static random access memory device according to claim 9 wherein increasing the time constant comprises adding a plurality of resistors that have a combined resistance value of approximately 4 mega ohms.

11. In a field programmable gate array circuit, a method of increasing radiation tolerance in a static random access memory device comprising:

determining a recovery time period of the static random access memory device;

determining a RC time constant of the static random access memory device;

comparing said recovery time period to said RC time constant;

increasing at least one of a resistance and a capacitance of the static random access memory device, if said recovery time period is greater than said RC time constant.

12. The method of increasing radiation tolerance in a static random access memory device according to claim 11 , wherein increasing at least one of a resistance and a capacitance of the static random access memory device further includes adding a resistor to the static random access memory device.

13. The method of increasing radiation tolerance in a static random access memory device according to claim 11 , wherein determining the recovery time period of the static random access memory device includes determining a time period required for the static random access memory device to recover from a high-energy particle strike.