Granted Patent B2

US 7,112,510 · App. 10/764,637 · Granted Sep 26, 2006

Abstract

Claims (30)

1. A method for forming a semiconductor device isolating barrier comprising:

forming a pad oxide layer and a nitride layer on a semiconductor substrate;

forming a trench region by etching the pad oxide layer and the nitride layer;

forming spacers at sidewalls of the etched pad oxide layer and the etched nitride layer;

forming a trench by etching the semiconductor substrate using the spacers and the etched nitride layer as a mask; and

after forming a liner oxide layer and a trench oxide layer filling the trench, forming the device isolating barrier by flattening the liner oxide layer and the trench oxide layer to expose the etched nitride layer.

2. A method as defined in claim 1 , wherein a thickness of the nitride layer ranges from about 500 to about 1000 Å.

3. The method of claim 1 , wherein said step of forming a trench region comprises the steps of:

forming a photoresist layer on the nitride layer;

removing a portion or the photoresist layer where a trench will be formed; and

etching the nitride layer and the pad oxide layer using the photoresist layer as a mask.

4. The method of claim 1 , wherein said step of forming spacers comprises the steps of:

after forming the trench region, forming a spacer oxide layer in the trench region and on the nitride layer; and

etching back the spacer oxide layer to leave the spacers at the sidewalls of the etched pad oxide layer and the etched nitride layer.

5. A method for forming a gate electrode of a semiconductor device comprising:

forming a pad oxide layer and a first nitride layer on a semiconductor substrate;

forming a trench region by etching the pad oxide layer and the first nitride layer;

forming spacers at sidewalls of the etched pad oxide layer and the etched first nitride layer;

forming a first trench by etching the semiconductor substrate using the spacers and the etched first nitride layer as a mask;

after forming a liner oxide layer and a trench oxide layer filling the trench, forming a device isolating barrier by flattening to liner oxide layer and the trench oxide layer the expose the etched first nitride layer;

after forming a second nitride layer on top of the etched first nitride layer, forming a second trench by etching the second nitride layer and the etched first nitride layer;

after a conducting layer is formed to fill the second trench, flattening the conducting layer to expose the second nitride layer; and

forming the gate electrode by removing the second nitride layer and the etched first nitride layer.

6. A method as defined in claim 5 , wherein a thickness of the first nitride layer ranges from about 500 to about 1000 Å.

7. A method as defined in claim 5 , wherein a thickness of the second nitride layer ranges from about 1000 to about 1500 Å.

8. A method as defined in claim 5 , wherein etching the second nitride layer and the etched first nitride layer comprises etching with an etching gas having a greater than a 7:1 selectivity of the first and second nitride layers with respect to the oxide layer.

9. A method as defined in claim 8 , wherein the etching gas comprises a mixture of CO, CHF 3 and C 4 F 8 .

10. A method as defined in claim 5 , comprising depositing the conducting layer through a LPCVD process at about 550 to about 650° C.

11. A method as defined in claim 10 , wherein a thickness of the deposited conducting layer ranges from 2000 to 5000 Å.

12. A method as defined in claim 5 , wherein flattening the conducting layer comprises performing a chemical mechanical polishing process, and wherein a thickness of the nitride layer left after the flattening process ranges from about 10 to about 90% of a thickness of the nitride layer before the flattening.

Assignments (8)