High speed non-volatile electronic memory configuration
View Patent ↗A high speed non-volatile electronic memory configuration and method is disclosed. In one particular exemplary embodiment, the high speed non-volatile electronic memory configuration may be realized comprising a high speed volatile memory, a non-volatile memory coupled to the high speed volatile memory, a controller coupled to the high speed volatile memory and the non-volatile memory, and a power level detector that detects when power is above a particular minimum operating voltage level. The controller monitors data storage changes made within the high speed volatile memory and controls the transfer of stored data from the high speed volatile memory to the non-volatile memory, and vice-versa, when power is above the particular minimum operating voltage level.
1. A non-volatile electronic memory configuration comprising:
a volatile memory having a first port and a second port;
a non-volatile memory coupled to the second port of the volatile memory;
a controller coupled to both the first port and the second port of the volatile memory and the non-volatile memory to monitor data storage changes made within the volatile memory and control the transfer of stored data from the volatile memory to the non-volatile memory, and vice-versa, based upon the monitored data storage changes when power is above a particular minimum operating voltage level; and
a power level detector that detects when power is above the particular minimum operating voltage level.
2. The configuration of claim 1 , further comprising:
a power storage element that stores transient power for use by at least one of the volatile memory, the non-volatile memory, and the controller when power is below the particular minimum operating voltage level.
3. The configuration of claim 2 , wherein the controller controls the transfer of stored data from the volatile memory to the non-volatile memory based upon the monitored data storage changes for a limited period of time using the transient power stored by the power storage element when power is below the particular minimum operating voltage level.
4. The configuration of claim 2 , wherein the power storage element comprises bulk capacitance having a value in the hundreds of microfarads.
5. The configuration of claim 1 , wherein the volatile memory is a dynamic random access memory.
6. The configuration of claim 1 , wherein the controller monitors data storage changes made within the volatile memory via the first port.
7. The configuration of claim 1 , wherein the controller controls the transfer of stored data from the second port of the volatile memory to the non-volatile memory.
8. The configuration of claim 1 , wherein the non-volatile memory operates at a lower speed than the volatile memory.
9. The configuration of claim 1 , wherein the non-volatile memory is a non-volatile flash memory.
10. The configuration of claim 1 , wherein the controller is one of a microprocessor, a microcontroller, a programmable processing device, and a fixed function processing device.
11. The configuration of claim 1 , wherein the controller prevents the transfer of stored data from the volatile memory to the non-volatile memory, and vice-versa, when power is below the particular minimum operating voltage level for more than a limited period of time.
12. The configuration of claim 1 , wherein the controller controls the transfer of stored data from the non-volatile memory to the volatile memory immediately following a restoration of power to above the particular minimum operating voltage level.
13. The configuration of claim 1 , wherein the power level detector provides an indication to the controller that power is above the particular minimum operating voltage level.
14. A method for controlling data storage, the method comprising:
monitoring data storage changes made within a volatile memory having a first port and a second port, wherein the data storage changes made within the volatile memory via the first port are monitored;
controlling the transfer of stored data from the second port of the volatile memory to a non-volatile memory, and vice-versa, based upon the monitored data storage changes when power is above a particular minimum operating voltage level; and
preventing stored data from being transferred from the second port of the volatile memory to the non-volatile memory, and vice-versa, when power is below the particular minimum operating voltage level.
15. The method of claim 14 , further comprising:
detecting when power is above the particular minimum operating voltage level.
16. The method of claim 15 , further comprising:
providing an indication that power is above the particular minimum operating voltage level.
17. The method of claim 14 , further comprising:
detecting when power is below the particular minimum operating voltage level.
18. The method of claim 17 , further comprising:
providing an indication that power is below the particular minimum operating voltage level.
19. The method of claim 18 , further comprising:
providing a transient power when power is below the particular minimum operating voltage level; and
controlling the transfer of stored data from the second port of the volatile memory to the non-volatile memory based upon the monitored data storage changes for a limited period of time using the transient power when power is below the particular minimum operating voltage level.
20. The method of claim 14 , further comprising:
controlling the transfer of stored data from the non-volatile memory to the second port of the volatile memory immediately following a restoration of power to above the particular minimum operating voltage level.