Integrated circuit delivering logic levels at a voltage independent from the mains voltage, with no attached regulator for the power section, and corresponding communication module
View Patent ↗The invention concerns an integrated circuit comprising means of delivering, on at least one output, a predetermined output voltage representative of a logic level, means of distributing a mains voltage and means of generating an internal voltage reference lower than the mains voltage, comprising means of connecting the mains voltage to the output and means of limiting and/or detecting the voltage at the output at the predetermined output voltage value, taking into account the reference voltage.
1. Integrated circuit comprising means of delivering to at least one output a predetermined output voltage representative of a logic level, which comprises means of generating a main voltage and means of generating a reference voltage lower than the main voltage, characterized in that it comprises
a first transistor connecting the main voltage on the output, and
means of limiting and/or detecting the voltage on the output at the value of the predetermined output voltage, equal to the reference voltage, and which comprises at least a second transistor having a gate connected to the gate of a third transistor mounted as a diode at the reference voltage, the limiting means comprising means of blocking the first transistor when the predetermined voltage is reached, and the blocking means having first and second mirrors connected to each other.
2. Integrated circuit according to claim 1 , characterized in that, when the predetermined voltage is reached, the currents circulating in the first transistor and in the limiting and/or detecting means are comprised in the region of a few dozen μA.
3. Integrated circuit according to claim 1 , characterized in that the first transistor comprises a first power transistor.
4. Integrated circuit according to claim 3 , characterized in that the drain of the first power transistor is connected to the output and its source to the main voltage.
5. Integrated circuit according to claim 1 , characterized in that the first current mirror delivers a blocking current when the predetermined voltage is reached on the output, and in that the second mirror sends a copy of the blocking current to the gate of the first power transistor, so as to block it.
6. Integrated circuit according to claim 3 , characterized in that the gate of the first power transistor is connected to a command input via a fourth transistor.
7. Integrated circuit according to claim 6 , characterized in that the fourth transistor is weaker than the transistors of the second mirror, so that the latter imposes its level on the fourth transistor when it delivers the copy of the blocking current.
8. Integrated circuit according to claim 1 , characterized in that the output voltage corresponds to the logic level “1” of a USB connection.
9. Integrated circuit according to claim 1 , characterized in that the reference voltage is used to supply the logic CMOS section of the integrated circuit.
10. Integrated circuit according to claim 1 , characterized in that the reference voltage and/or the predetermined voltage have the value of 3 V, the main voltage having a value of 5 V.
11. Communication module for an integrated circuit comprising means of delivering, on at least one output, a predetermined output voltage representative of a logic level, which comprise means of generating a main voltage and means of generating a reference voltage lower than the main voltage, characterized in that it comprises
a first transistor connecting the main voltage to the output, and
means of limiting the voltage on the output at the predetermined output voltage value, which comprises at least a second transistor having a gate connected to the gate of a third transistor mounted as a diode at the reference voltage, the limiting means comprising means of blocking the first transistor when the predetermined voltage is reached, and the blocking means having first and second mirrors connected to each other.
12. Integrated circuit comprising means of delivering to at least one output a predetermined output voltage representative of a logic level, which comprise means of generating a main voltage and means of generating a reference voltage lower than the main voltage, characterized in that it comprises
means of connecting the main voltage on the output, which comprise a first power transistor, and
means of limiting and/or detecting the voltage on the output at the value of the predetermined output voltage, taking into account the reference voltage,
the limiting means comprising means of blocking the first power transistor when the predetermined voltage is reached,
the blocking means have first and second current mirrors connected to each other,
the first current mirror delivers a blocking current when the predetermined voltage is reached on the output, and in that the second mirror sends a copy of the blocking current to the gate of the first power transistor so as to block it,
the gate of the first power transistor being connected to a command input via a fourth transistor,
the fourth transistor is weaker than the transistors of the second mirror, so that the later imposes its level on the fourth transistor when it delivers the copy of the blocking current.
13. Integrated circuit comprising means of delivering to at least one output a predetermined output voltage representative of a logic level, which comprises means of generating a main voltage and means of generating a reference voltage lower than the main voltage, and comprising:
means of connecting the main voltage on the output and comprising a first power transistor, and
means of limiting and/or detecting the voltage on the output at the value of the predetermined output voltage, equal to the reference voltage, and comprising means of blocking the first power transistor when the predetermined voltage is reached, the means of blocking comprising first and second current mirrors connected to each other.
14. Integrated circuit comprising means of delivering to at least one output a predetermined output voltage representative of a logic level, which comprises means of generating a main voltage and means of generating a reference voltage lower than the main voltage, and comprising:
means of connecting the main voltage on the output, and
means of limiting and/or detecting the voltage on the output at the value of the predetermined output voltage, equal to the reference voltage, and which comprises means of blocking the means of connecting when the predetermined voltage is reached, wherein the means of blocking comprises a first current mirror that delivers a blocking current when the predetermined voltage is reached on the output and a second current mirror that sends a copy of the blocking current to the means of connecting, so as to block the means of connecting.