Structure and fabrication method for capacitors integratible with vertical replacement gate transistors
View Patent ↗A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.
1. An integrated circuit structure comprising:
a semiconductor layer having a major surface formed along a plane;
a first doped region of a first conductivity type in a first area of the surface;
multiple layers over the first doped region, wherein the multiple layers define a window therein extending to the first doped region;
a second doped region of a second conductivity type in the window;
a third doped region of the first conductivity type over the second doped region;
a gate oxide adjacent the second doped region;
a first conductive layer comprising first and second laterally disposed regions, wherein the first region is adjacent the gate oxide, and wherein the second region is spaced apart from the gate oxide in a second area of the surface;
a first dielectric layer overlying and in contact with the second region;
a second conductive layer over the first dielectric layer;
an insulator interposed between the first and the second regions of the first conductive layer so as to electrically isolate the first and the second regions; and
wherein the first region, the second region, and the second conductive layer are electrically independent.
2. The integrated circuit structure of claim 1 wherein the insulator is selected from the group comprising silicon dioxide, silicon nitride and air.
3. The integrated circuit structure of claim 1 wherein the first conductive layer is selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped silicon-germanium, doped silicon-germanium-carbon, metals and metal compounds.
4. The integrated circuit structure of claim 1 wherein the material of the first dielectric layer is selected from among silicon dioxide and silicon nitride.
5. The integrated circuit structure of claim 1 further comprising a second dielectric layer over the second conductive layer, wherein the second dielectric layer includes at least one via therein for providing conductive access to at least one of the second region and the second conductive layer.
6. An integrated structure comprising:
a semiconductor layer having a major surface formed along a plane;
a first doped region of a first conductivity type in a first area of the surface;
multiple layers over the surface, wherein the multiple layers have a first window therein extending to the first doped region;
a second doped region of a second conductivity type in the window;
a third doped region of the first conductivity type over the second doped region;
an oxide layer adjacent the second doped region;
a first conductive layer in contact with the oxide layer;
a second window within one or more of the multiple layers, wherein the second window is spaced apart from the first window, the second window comprising sidewall surfaces and a bottom surface;
a second conductive layer laterally proximate the first conductive layer;
within the second window, a third conductive layer substantially conformal with the sidewall surfaces and the bottom surface of the the second window and electrically connected to the second conductive layer;
a conformal dielectric layer over the third conductive layer; and
a fourth conductive layer over the dielectric layer, such that the fourth conductive layer, the dielectric layer and the third conductive layer form a capacitor within the second window.
7. An integrated structure comprising:
a semiconductor layer having a major surface formed along a plane;
a first doped region of a first conductivity type in a first area of the surface;
multiple layers over the surface, wherein the multiple layers have a first window therein extending to the first doped region;
a second doped region of a second conductivity type in the window;
a third doped region of the first conductivity type over the second doped region;
an oxide layer adjacent the second doped region;
a second window within one or more of the multiple layers, wherein the second window is spaced apart from the first window, the second window comprising sidewall surfaces and a bottom surface;
a second conductive layer laterally proximate the first conductive layer;
within the second window, a third conductive layer substantially conformal with the sidewall surfaces and the bottom surface of the second window and electrically connected to the second conductive layer;
a conformal dielectric layer within the second window and over the third conductive layer; and
a fourth conductive layer over the dielectric layer, such that the fourth conductive layer, the dielectric layer and the third conductive layer form a capacitor wherein the first conductive layer comprises a gate of the MOSFET, and wherein the third conductive layer comprises a capacitor plate.
8. The integrated circuit structure of claim 7 wherein the material of the first conductive layer is selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped silicon-germanium, doped silicon-germanium-carbon, metals and metal compounds.
9. The integrated circuit structure of claim 7 wherein the material comprising the dielectric layer is selected from among silicon dioxide and silicon nitride.
10. The integrated circuit structure of claim 7 further comprising an insulator material disposed between the first and the second conductive layers.