Complementary code keying (CCK) sequentially decoding apparatus and process thereof
View Patent ↗An apparatus of sequentially decoding CCK codes includes a series of received signal registers used to respectively temporarily save the received signals, a phase selector used to select one numeral from 1, −1, j or −j respectively for CCK code of each chip to multiple with the signal register, a series of adders used to sequentially complete adding operation, a series of sequential operation registers used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders, and a comparing device used to select a maximal value from those saved in the operation registers. The comparing device includes a comparator and a maximum register. According to the invention, the data processing speeds up while the hardware complexity is reduced.
1. A process of sequentially decoding complementary code keying (CCK) codes, applicable in CCK code correlation in a wireless network, the process comprising:
receiving and saving a first input signal in a first signal register (Xo) and then the first signal multiplying with one selected from 1, −1, j or −j according to the first set of CCK codes of No. 0 chip (C 0 — 1 ), this product being saved in the first operation register (R 0 );
receiving and saving a second input signal in a second signal register (X 1 ) and then the second signal multiplying with one selected from 1, −1, j or −j according to a first set of CCK codes of No. 1 chip (C 1 — 1 ), this product and the value of the first operation register (R 0 ) adding up to save in a second operation register (R 1 );
receiving and saving a third input signal in a third signal register (X 2 ), and then the third signal multiplying with 1, −1, j or j according to a first set of CCK codes of No. 2 chip (C 2 — 1 ), this product and the value of the second operation register (R 1 ) adding up to save in a third operation register (R 2 );
receiving and saving a fourth input signal in a fourth signal register (X 3 ), and then the fourth signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 3 chip (C 3 — 1 ), this product and the value of the third operation register (R 2 ) adding up to save in a fourth operation register (R 3 );
receiving and saving a fifth input signal in a fifth signal register (X 4 ), and then the fifth input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 4 chip (C 4 — 1 ), this product and the value of the fourth operation register (R 3 ) adding up to save in a fifth operation register (R 4 )
receiving and saving a sixth input signal in a sixth signal register (X 5 ), and then the sixth input signal multiplying with 1, −1, j or j according to a first set of CCK codes of No. 5 chip (C 5 — 1 ), this product and the value of the fifth operation register (R 4 ) adding up to save in a sixth operation register (R 5 );
receiving and saving a seventh input signal in a seventh signal register (X 6 ), and then the seventh input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 6 chip (C 6 — 1 ), this product and the value of the sixth operation register (R 5 ) adding up to save in a seventh operation register (R 6 ); and
receiving and saving an eighth input signal in an eighth signal register(X 7 ), and then the eighth input signal multiplying with 1, −1, j or −j according to a first set of CCK codes of No. 7 chip(C 7 — 1 ), this product and the value saved in the seventh operation register(R 6 ) adding up to save in an eighth operation register (R 7 ).
2. The process of claim 1 , further comprising:
after the second signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 0 chip (C 0 — 2 ) to multiple with the first signal register (X 0 ), the product being saved in the first operation register (R 0 );
after the third signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 1 chip (C 1 — 2 ) to multiple with the value of the second signal register(X 1 ), the product and the first operation register(R 0 ) adding up to save in the second operation register (R 1 );
after the fourth signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 2 chip (C 2 — 2 ) to multiple with the value of the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 );
after the fifth signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 3 chip (C 3 — 2 ) to multiple with the value of the fourth signal register(X 3 ), the product and the third operation register(R 2 ) adding up to save in the fourth operation register (R 3 );
after the sixth signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 4 chip (C 4 — 2 ) to multiple with the value of the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 5 chip (C 5 — 2 ) to multiple with the value of the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
after the eighth signal has received, selecting one of 1, −1, j, or −j according to a second set of CCK codes of No. 6 chip (C 6 — 2 ) to multiple with the value of the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 ); and
selecting one of 1, −1, j, or −j is selected according to a second set of CCK codes of No. 7 chip (C 7 — 2 ) to multiple with the value of the eighth signal register (X 7 ), the product and the sixth operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
3. The process of claim 1 , further comprising:
after the third signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 0 chip (C 0 — 3 ) to multiple with the value of the first signal register (X 0 ), the product being saved in the first operation register (R 0 );
after the fourth signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 1 chip (C 1 — 3 ) to multiple with the value of the second signal register(X 1 ), the product and the first operation register(R 0 ) adding up to save in the second operation register (R 1 );
after the fifth signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 2 chip (C 2 — 3 ) to multiple with the value of the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 );
after the sixth signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 3 chip (C 3 — 3 ) to multiple with the value of the fourth signal register (X 3 ), the product and the value of third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 4 chip (C 4 — 3 ) to multiple with the value of the fifth signal register (X 4 ), the product and the value of the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
after the eighth signal has been received, selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 5 chip (C 5 — 3 ) to multiple with the value of the sixth signal register (X 5 ), the product and the value of the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 6 chip (C 6 — 3 ) to multiple with the value of the seventh signal register (X 6 ), the product and the value of the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 ); and
selecting one of 1, −1, j, or −j according to a third set of CCK codes of No. 7 chip (C 7 — 3 ) to multiple with the eighth signal register (X 7 ), the product and the value of the seventh operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
4. The process of claim 1 , further comprising:
after the fourth signal has been received, selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 0 chip (C 0 — 4 ) to multiple with the value of first signal register (X 0 ), the product being saved in the first operation register (R 0 );
after the fifth signal has been received, selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 1 chip(C 1 — 4 ) to multiple with the second signal register(X 1 ), the product and the value of first operation register (R 0 ) adding up to save in the second operation register (R 1 );
after the sixth signal has been received, selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 2 chip (C 2 — 4 ) to multiple with the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 );
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 3 chip (C 3 — 4 ) to multiple with the fourth signal register (X 3 ), the product and the third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
after the eighth signal has been received, selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 4 chip (C 4 — 4 ) to multiple with the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
selecting one of 1, −1, j, or −j according to a fourth set of CCK codes of No. 5 chip (C 5 — 4 ) to multiple with the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1,j, or −j according to a fourth set of CCK codes of No. 6 chip(C 6 — 4 ) to multiple with the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 ); and
selecting one of 1, −1,j, or −j according to a fourth set of CCK codes of No. 7 chip (C 7 — 4 ) to multiple with the eighth signal register (X 7 ), the product adding up the seventh operation register (R 6 ) and the obtained sum is saved in the eighth operation register (R 7 ).
5. The process of claim 1 , further comprising:
after the fifth signal has been received, selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 0 chip (C 0 — 5 ) to multiple with the first signal register (X 0 ), the product being is saved in the first operation register (R 0 );
after the sixth signal has been received, selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 1 chip (C 1 — 5 ) to multiple with the second signal register (X 1 ), the product and the first operation register(R 0 ) adding up to save in the second operation register (R 1 );
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 2 chip (C 2 — 5 ) to multiple with the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 );
after the eighth signal has been received, selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 3 chip (C 3 — 5 ) to multiple with the fourth signal register (X 3 ), the product and the third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
selecting one of 1, −1, j, −j according to a fifth set of CCK codes of No. 4 chip (C 4 — 5 ) to multiple with the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 ),
selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 5 chip (C 5 — 5 ) to multiple with the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 6 chip (C 6 — 5 ) to multiple with the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 );
selecting one of 1, −1, j, or −j according to a fifth set of CCK codes of No. 7 chip (C 7 — 5 ) to multiple with the eighth signal register (X 7 ), the product and the seventh operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
6. The process of claim 1 , further comprising:
after the sixth signal has been received, selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 0 chip (C 0 — 6 ) to multiple with the first signal register (X 0 ), the product being saved in the first operation register (R 0 );
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 1 chip (C 1 — 6 ) to multiple with the second signal register (X 1 ), the product and the first operation register (R 0 ) adding up to save in the second operation register (R 1 );
after the eighth signal has been received, selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 2 chip (C 2 — 6 ) to multiple with the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 );
selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 3 chip (C 3 — 6 ) to multiple with the fourth signal register (X 3 ), the product and the third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 4 chip (C 4 — 6 ) to multiple with the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
selecting one of 1, −1,j, or −j according to a sixth set of CCK codes of No. 5 chip (C 6 — 6 ) to multiple with the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1, j, or −j according to a sixth set of CCK codes of No. 6 chip (C 6 — 6 ) to multiple with the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 ); and
selecting one of 1, −1, j, or −j is selected according to a sixth set of CCK codes of No. 7 chip (C 2 — 6 ) to multiple with the eighth signal register (X 7 ), the product and the seventh operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
7. The process of claim 1 , further comprising:
after the seventh signal has been received, selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 0 chip (C 0 — 7 ) to multiple with the first signal register (X 0 ), the product being saved in the first operation register (R 0 );
after the eighth signal has been received, selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 1 chip (C 1 — 7 ) to multiple with the second signal register (X 1 ), the product and the first operation register (R 0 ) adding up to save in the second operation register (R 1 );
selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 2 chip (C 2 — 7 ) to multiple with the third signal register(X 2 ), the product and the second operation register(R 1 ) adding up to save in the third operation register (R 2 )
selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 3 chip (C 3 — 7 ) to multiple with the fourth signal register (X 3 ), the product and the third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 4 chip (C 4 — 7 ) to multiple with the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. S chip (C 5 — 7 ) to multiple with the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1, j, or −j is selected according to a seventh set of CCK codes of No. 6 chip (C 6 — 7 ) to multiple with the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 );
selecting one of 1, −1, j, or −j according to a seventh set of CCK codes of No. 7 chip (C 7 — 7 )to multiple with the eighth signal register (X 7 ), the product and the seventh operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
8. The process of claim 1 , further comprising:
after the eighth signal has been received, one of 1, −1, j, or −j is selected according to an eighth seventh set of CCK codes of No. 0 chip (Cog) to multiple with the first signal register (X 3 ), the product being saved in the first operation register (R 0 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 1 chip (C 1 — 8 ) to multiple with the second signal register (X 1 ), the product and the first operation register (R 0 ) adding up to save in the second operation register (R 1 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 2 chip (C 2 — 3 ) to multiple with the third signal register (X 2 ), the product and the second operation register (R 1 ) adding up to save in the third operation register (R 2 )
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 3 chip (C 3 — 8 ) to multiple with the fourth signal register (X 3 ), the product and the third operation register (R 2 ) adding up to save in the fourth operation register (R 3 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 4 chip (C 4 — 8 ) to multiple with the fifth signal register (X 4 ), the product and the fourth operation register (R 3 ) adding up to save in the fifth operation register (R 4 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 5 chip (C 5 — 8 ) to multiple with the sixth signal register (X 5 ), the product and the fifth operation register (R 4 ) adding up to save in the sixth operation register (R 5 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 6 chip (C 6 — 8 ) to multiple with the seventh signal register (X 6 ), the product and the sixth operation register (R 5 ) adding up to save in the seventh operation register (R 6 );
selecting one of 1, −1, j, or −j according to an eighth set of CCK codes of No. 7 chip (C 7 — 8 )to multiple with the eighth signal register(X 7 ), the product and the seventh operation register (R 6 ) adding up to save in the eighth operation register (R 7 ).
9. The process of claim 1 , further comprising:
sequentially the values saved in the eighth operation registers (R 7 ) to retrieve the maximal one; and
saving the maximal value in the maximal register (R 8 ).
10. An apparatus of sequentially decoding CCK codes, applicable in calculating the correlation between CCK codes, the apparatus comprising:
a series of received signal registers(X 0 ′ X 1 ′ X 2 ′ X 3 ′ X 4 ′ X 5 ′ X 6 ′ X 7 ) used to respectively temporarily save the received signals, wherein the received signal registers include a first signal register X 0 , a second signal register X 1 , a third signal register X 2 , a fourth signal register X 3 , a fifth signal register X 4 , a sixth signal register X 5 , a seventh signal register X 6 and a eight signal register X 7 ;
a phase selector used to select one numeral from 1, −1,j or −j respectively for CCK code of each chip to multiple with the signal register;
a series of adders (Adder 1 , Adder 2 , Adder 3 , Adder 4 , Adder 5 , Adder 6 and Adder 7 ) used to sequentially complete adding operation;
a series of sequential operation registers (R 0 , R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 ) used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders; and
a comparing device used to select a maximal value from those saved in the operation registers, wherein the comparing device includes a comparator and a maximum register (R 8 ).
wherein the received signal registers include a first signal register X 0 , a second signal register X 1 , a third signal register X 2 , a fourth signal register X 3 , a fifth signal register X 4 , a sixth signal register X 5 , a seventh signal register X 6 and a eighth signal register X 7 ;
wherein the sequential operation registers include a first operation register R 0 , a second operation register R 1 , a third operation register R 2 , a fourth operation register R 3 , a fifth operation register R 4 , a sixth operation register R 5 , a seventh operation register R 6 and a eighth operation register R 7 ;
wherein the adders include a first adder Adder 1 , a second Adder 2 , a third adder Adder 3 , a fourth Adder 4 , a fifth Adder 5 , a sixth Adder 6 , and a seventh Adder 7 ; and
wherein X 0 is subjected to the phase selection and multiplication and then the result is saved in R 0 ; Adder 1 adds up R 0 and the product of X 1 multiplying with a selected phase (1, −1, j, −j) and saves the obtained sum in R 1 ; Adder adds up R 1 and the product of X 2 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 2 ; Adder 3 adds up R 7 and the product of X 3 multiplying with a selected phase (1, −1, j, −j) and saves the obtained sum in R 3 ; Adder 4 adds up R and the product of X 4 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 4 , Adder 5 adds up R4 and the product of X5 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 5 ; Adder 6 adds up R 5 and the product of X 6 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 6 ; Adder 7 adds up R 6 and the product of X 7 multiplying with a selected phase (1, −1−j,−j), and saves the obtained sum is saved in R 7 .
11. The apparatus of claim 10 , wherein the comparator is a 2-to-1 comparator.
12. A system of sequentially decoding CCK codes, which is applied to calculate CCK code correlation in a wireless network, the system comprising:
a series of received signal registers (X 0 , X 1 , X 2 , X 3 , X 4 , X 5 , X 6 , X 7 ) to temporarily save received signals;
a first sequentially decoding module for sequentially decoding CCK codes according to the received signals;
a second sequentially decoding module used to for sequentially decoding CCK codes according to the received signals;
a third sequentially decoding module used to for sequentially decoding CCK codes according to the received signals;
a fourth sequentially decoding module used to for sequentially decoding CCK codes according to the received signals;
a fifth sequentially decoding module used to for sequentially decoding CCK codes according to the received signals;
a sixth sequentially decoding module used to for sequentially decoding CCK codes according to the received signals;
a seventh sequentially decoding module used to for sequentially decoding CCK codes according to the received signals; and
an eighth sequentially decoding module used to for sequentially decoding CCK codes according to the received signals
wherein each sequentially decoding module comprises:
a phase selector used to select one of 1, −1, j or −j according to CCK code of each chip to multiple with the corresponding value of the register;
a series of adders (Adder 1 , Adder 2 , Adder 3 , Adder 4 , Adder 5 , Adder 6 and Adder 7 ) used to complete the adding operation in sequence;
a series of sequential operation registers (R 0 , R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , and R 7 ) is used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders;
a comparing device used to select a maximal value among those saved in the operation registers, the comparing device including a comparator and a maximum register (R 8 );
wherein the received signal registers include a first signal register X 0 , a second signal register X 1 , a third signal register X 2 , a fourth signal register X 3 , a fifth signal register X 4 , a sixth signal register X 4 , a seventh signal register X 6 and a eighth signal register X 7 ,
wherein the sequential operation registers include a first operation register R, a second operation register R 1 , a third operation register R 2 , a fourt operation register R 3 , a fifth operation register R 4 , a sixth operation register R 5 , a seventh operation register R 6 and a eighth operation register R 7 ;
wherein the adders include a first adder Adder 1 , a second Adder 2 , a third adder Adder 3 , a fourth Adder 4 , a fifth Adder 5 , a sixth Adder 6 and a seventh Adder 7 ;
wherein X 0 is subjected to the phase selection and multiplication and then the result is saved in R 0 ; Adder 1 adds up R 0 and the product of X 1 multiplying with a selected phase (1, −1, j, −j) and saves the obtained sum in R 1 ; Adder 2 adds up R 1 and the product of X 2 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 2 ; Adder 3 adds up R 2 and the product of X 3 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 3 ; Adder 4 adds up R 3 and the product of X 4 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R4; Adder 5 adds up R 4 and the product of X 5 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum in R 5 ; Adder 6 adds up R 5 and the product of X 6 multiplying with a selected phase (1, −1, j −j), and saves the obtained sum in R 6 ; Adder 7 adds up R 6 and the product of X 7 multiplying with a selected phase (1, −1, j, −j), and saves the obtained sum is saved R 7 .
13. The apparatus of claim 12 , wherein the comparator is a 2-to-1 comparator.