Spread spectrum controllable delay clock buffer with zero cycle slip
View Patent ↗A controllable delay clock buffer that provides spread spectrum modulation of the output signals with zero cycle slip includes a PLL having a PLL loop filter that comprises an RC network. A clock signal is input to the PLL, and a SS modulation frequency is injected into the capacitor of the PLL loop filter. The SS signal is provided by a secondary charge pump that produces a programmable waveform such as a square wave or a stair case square wave current signal. The programmable waveform is integrated by the loop filter capacitor to form a corresponding triangular or trigonal waveform which varies the input to the VCO of the PLL to define a frequency modulation profile that has a corresponding triangular or trigonal envelope. The bandpass profile of the SS modulation signal is at a higher frequency range than the lowpass profile of the PLL, so that the SS waveform profile is not distorted or cancelled by the PLL.
1. A method for generating a spread spectrum clock signal, including the steps of:
providing a phase lock loop;
inputting a constant clock input signal to said phase lock loop;
injecting a spread spectrum modulating signal into said phase lock loop;
controlling said phase lock loop so that there is a net zero cycle slip between said spread spectrum clock signal and said constant clock input signal;
wherein:
Cycle
slip
occurs
i
f
T
wander
T
clk
>
1
and
+
_
T
wander
T
clk
=
+
_
∂
[
F
clk
4
·
F
mr
]
wherein ±∂ is the peak percentage frequency deviation,
F CLK is the clock frequency=1/T CLK , where
T CLK is the clock period,
Twander is the varying displacement between corresponding rising edges of said spread spectrum clock signal and said constant clock input signal, and
F MR is the modulation rate.