Electrostatic discharge protection circuit

1. A protection circuit for protecting an electronic circuit from an electrostatic discharge (ESD) event, the electronic circuit, in operation, being supplied a supply voltage via a supply voltage terminal, with respect to a reference voltage, the reference voltage being supplied via a reference voltage terminal, the protection circuit comprising:

a set of at least two bipolar transistors coupled in series, each two neighboring transistors being coupled with respective first connections between a collector of one transistor and an emitter of the other transistor, the set of at least two transistors being further coupled with the supply voltage terminal and the reference voltage terminal, a first of the transistors being directly coupled with the supply voltage terminal and a second of the transistors being directly coupled with the reference voltage terminal,

wherein the bases of every two neighboring transistors are interconnected by respective second connections,

wherein the second connections between the bases each consist of two resistances coupled in series through respective third connections, and

wherein respective fourth connections couple the respective first and third connections.

2. The protection circuit of claim 1 , wherein set of bipolar transistors comprises a set of NPN transistors.

3. The protection circuit of claim 1 , wherein the set of bipolar transistors comprises a set of PNP transistors.

4. The protection circuit of claim 1 , further comprising one or more capacitors, each capacitor being coupled between the supply voltage terminal, to which one of the transistors is directly connected, and the base of one or more of the other transistors.

5. A device according to claim 1 , further comprising one or more gate coupled double-diffused metal-oxide-semiconductor (DMOS) transistors, each DMOS transistor being coupled between the supply voltage terminal, to which one of the transistors is directly connected, and the base of one or more of the other transistors.

6. An electronic device that, in operation, is supplied a supply voltage via a supply voltage terminal, with respect to a reference voltage, and the reference voltage is supplied via a reference voltage terminal, the electronic device including a protection circuit comprising:

a set of at least two bipolar transistors coupled in series, each two neighboring transistors being coupled with respective first connections between a collector of one transistor and an emitter of the other transistor, the set of at least two transistors being further coupled with the supply voltage terminal and the reference voltage terminal, a first of the transistors being directly coupled with the supply voltage terminal and a second of the transistors being directly coupled with the reference voltage terminal,

wherein the bases of every two neighboring transistors are interconnected by respective second connections,

wherein the second connections between the bases each consist of two resistances coupled in series through respective third connections, and

wherein respective fourth connections couple the respective first and third connections.

7. An electrostatic discharge (ESD) protection circuit comprising:

a first NPN transistor;

a second NPN transistor, wherein a collector of the second NPN transistor is coupled with an emitter of the first NPN transistor via a first connector;

a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled with a base of the first NPN transistor via a second connector;

a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is connected to the second terminal of the first resistor via a third connector and the second terminal of the second resistor is coupled with a base of the second NPN transistor via a fourth connector; and

a fifth connector coupling the first connector with the third connector.

8. The ESD protection circuit of claim 7 , wherein a collector of the first NPN transistor is coupled with a power supply terminal of an electronic circuit and an emitter of the second NPN transistor is coupled with a reference voltage terminal of the electronic circuit.

9. The ESD protection circuit of claim 7 , wherein the electronic circuit comprises an integrated circuit.

10. The ESD protection circuit of claim 7 , wherein the power supply terminal comprises a power supply bus and the reference voltage terminal comprise a reference voltage bus.

11. The protection circuit of claim 7 , wherein respective resistance values of the first and second resistors are selected such that the protection circuit has a holding voltage of greater than 50 volts.

12. The protection circuit of claim 7 , further comprising:

a third NPN transistor, wherein a collector or the third NPN transistor is coupled with an emitter of the second NPN transistor via a sixth connector;

a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled with the base of the second NPN transistor via a seventh connector;

a fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled with the second terminal of the third resistor via an eighth connector and the second terminal of the fourth resistor is coupled with a base of the third NPN transistor via a ninth connector; and

a tenth connector coupling the sixth connector with the eighth connector.

13. The circuit of claim 7 , further comprising a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled with a collector of the first NPN transistor and the second terminal of the capacitor is coupled with the base of the second transistor.

14. The circuit of claim 7 , further comprising a double-diffused metal-oxide-semiconductor (DMOS) transistor having a drain, a source and a gate, the drain being coupled with a collector of the first NPN transistor, the source being coupled with tie base of the second NPN transistor, and the gate being coupled with the base of the second NPN transistor.

15. The protection circuit of claim 14 , wherein the DMOS transistor comprises a gate-coupled vertical-DMOS (VDMOS) transistor.

16. The protection circuit of claim 14 , wherein tie gate of the VDMOS transistor is coupled with the base of the second NPN transistor via a third and a fourth resistor and the source of the VDMOS transistor is coupled with the base of the second NPN transistor via the fourth resistor.

17. A method of protecting an electronic circuit from an electrostatic discharge (ESD) event, the method comprising:

providing a protection circuit coupled between a supply voltage terminal and a reference voltage terminal of the electronic circuit;

receiving an ESD pulse at a base-collector junction of a first NPN transistor of the protection circuit, the ESD pulse causing breakdown of the base-collector junction, resulting in snap-back of the first NPN transistor;

communicating current from the base of the first NPN transistor to a base of a second NPN transistor using a voltage divider consisting of a first resistance and a second resistance;

diverting at least a portion of the current between the first resistance and the second resistance to an emitter of the first NPN transistor and a collector of the second NPN transistor; and

controlling the current communicated from the base of the first NPN transistor to the base of the second NPN transistor with resistance values of the first resistance and the second resistance.

18. The method of claim 17 , further comprising controlling dynamic overshoot signals from the supply voltage terminal applied to the base of the second NPN transistor.