Chip scale package with open substrate

1. A method of manufacturing an integrated circuit package comprising:

forming a substrate including:

forming a core layer;

forming a through opening and vias in the core layer;

forming a first conductive layer on the core layer covering the through opening;

forming a second conductive layer on the core layer opposite the first conductive layer, the second conductive layer formed in the through opening and in the vias contacting the first conductive layer;

bonding an integrated circuit die to the second conductive layer and in the through opening;

forming connections between the integrated circuit die and the second conductive layer; and

encapsulating the integrated circuit die and the connections.

2. The method as claimed in claim 1 wherein:

forming the first conductive layer into terminals and a ground or thermal pad, the terminals extending out from the core layer; and

forming the second conductive layer into an integrated circuit die bonded portion and terminals.

3. The method as claimed in claim 1 wherein:

forming the first conductive layer into terminals and a ground or thermal pad;

forming the second conductive layer into an integrated circuit die bonded portion and terminals; and

forming the terminals of the first and second conductive layers to have a shape of at least one of square, rectangular, and round.

4. The method as claimed in claim 1 wherein:

forming the second conductive layer into terminals and a ground or thermal pad; and

further comprising:

forming solder balls connected to the terminals in a plurality of rows.

5. The method as claimed in claim 1 wherein:

forming the first conductive layer forms a ground or thermal pad;

forming the second conductive layer into an integrated circuit die bonded portion and terminals; and

further comprising:

forming solder balls connected to the terminals.

6. The method as claimed in claim 1 wherein forming the second conductive layer forms blind vias in the vias.

7. The method as claimed in claim 1 wherein forming the first conductive layer forms a plurality of rows of terminals.

8. The method as claimed in claim 1 wherein forming the first conductive layer forms a plurality of terminals having at least one shape from a rectangle, square, and circle.

9. The method as claimed in claim 1 further comprising forming a solder mask over at least one of the first and second conductive layer.

10. The method as claimed in claim 1 further comprising:

forming a second substrate including:

forming a core layer;

forming a through opening and vias in the core layer;

forming a first conductive layer on the bottom of the core layer covering the through opening;

forming a second conductive layer on the top of the core layer, the second conductive layer formed in the through opening and in the vias contacting the first conductive layer, the second conductive layer in the vias formed into terminals;

bonding a second integrated circuit die to the second conductive layer of the second substrate and in the through opening thereof;

forming second connections bonding the integrated circuit die to the second conductive layer of the second substrate;

encapsulating the second integrated circuit die and the second connections; and

wherein:

forming the first substrate includes the first conductive layer thereof formed into terminals extending from the core layer thereof;

forming the first and second substrates are bonded with the terminals of the first and second substrates electrically connected.

11. The method as claimed in claim 10 wherein:

bonding the first and second substrates by at least one of solder, solder balls, conductive adhesive, or a combination thereof.