IP Library Granted Patent US 7,160,810
Granted Patent B2
US 7,160,810 · App. 10/878,317 · Granted Jan 9, 2007

Method for forming interlayer insulation film in semiconductor device

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Quick Facts
Patent No.
US 7,160,810
App. No.
10/878,317
Granted
Jan 9, 2007
Kind
B2
Abstract

The present invention discloses a method for forming an interlayer insulation film in a semiconductor device, comprising the steps of: sequentially forming a porous low dielectric insulation film and a capping layer on the semiconductor substrate on which a few elements of the semiconductor device have been formed; and forming damascene patterns in the porous low dielectric insulation film by an etching process, and forming a protection film for closing pores exposed during the etching process at the same time.

Claims (30)

1. A method for forming an interlayer insulation film in a semiconductor device, comprising the steps of:

forming a diffusion barrier film on a lower interlayer insulation film and metal lines;

sequentially forming an upper interlayer insulation film and a capping layer on the diffusion barrier film; and

forming damascene patterns in the upper interlayer insulation film by an etching process, and forming a protection film for closing pores exposed during the etching process at the same time.

2. The method of claim 1 , wherein the upper interlayer insulation film is formed with using a porous organo silicate glass.

3. The method of claim 1 , wherein the capping layer is formed with polysilicon, SiO 2 , SiN, SiC or SiON, or a stacked structure thereof.

4. The method of claim 1 , wherein the protection film is formed with nonvolatile polymers.

5. The method of claim 4 , wherein an additive gas containing HBr gas and O 2 gas and CxHyFz gas are used at the same time to form the protection film during the etching process.

6. The method of claim 5 , wherein a supply flow of HBr gas ranges from 5 sccm to 1000 sccm, and a supply flow of 0 2 gas ranges from 1 sccm to 100 sccm.

7. The method of claim 5 , wherein a select ratio of the upper interlayer insulation film to the other materials is controlled by controlling a ratio of x to y and z in CxHyFz.

8. The method of claim 7 , wherein the select ratio of the materials excluding upper interlayer insulation film is increased by increasing the ratio of x to y and z, and decreased by decreasing the ratio of x to y and z.

9. The method of claim 5 , wherein N 2 , Ar or He gas is further supplied as the additive gas.

10. The method of claim 5 , wherein the select ratio of the materials excluding the upper interlayer insulation film is increased by decreasing an addition ratio of the additive gas, and decreased by increasing the addition ratio of the additive gas.

11. A method for forming an interlayer insulation film in a semiconductor device, comprising the steps of:

forming a lower interlayer insulation film on the semiconductor substrate on which a few elements of the semiconductor device have been formed;

forming damascene patterns in the lower interlayer insulation film using a dual damascene process;

forming a lower metal line by filling a conductive material in the damascene patterns, thereby forming a resulting structure;

forming a diffusion barrier layer on the resulting structure;

forming an upper interlayer insulation film on the diffusion barrier layer;

forming a capping layer on the upper interlayer insulation film;

performing an etching process to form a trench or via hall by etching the capping layer and the upper interlayer insulation film and to form a protective film on a sidewall of the trench or via hall; and

forming a upper metal line in the trench or via hail.

12. The method of claim 11 , wherein the protection film is formed with nonvolatile polymers.

13. The method of claim 12 , wherein an additive gas containing HBr gas and O 2 gas and CxHyFz gas are used at the same time to form the protection film during the etching process.

14. The method of claim 13 , wherein a supply flow of HBr gas ranges from 5 sccm to 1000 sccm, and a supply flow of O 2 gas ranges from 1 sccm to 100 sccm.

15. The method of claim 13 , wherein a select ratio of the upper interlayer insulation film to the other materials is controlled by controlling a ratio of x to y and z in CxHyFz.

16. The method of claim 15 , wherein the select ratio of the materials excluding the upper interlayer insulation film is increased by increasing the ratio of x to y and z, and decreased by decreasing the ratio of x to y and z.

17. The method of claim 13 , wherein N 2 , Ar or He gas is further supplied as the additive gas.

18. The method of claim 13 , wherein the select ratio of the materials excluding the upper interlayer insulation film is increased by decreasing an addition ratio of the additive gas, and decreased by increasing the addition ratio of the additive gas.

19. The method of claim 11 , wherein the upper interlayer insulation film includes a first insulation film, an etch barrier film on the first insulation film and a second insulation film on the etch barrier film.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2009
From: HYNIX SEMICONDUCTOR INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 022288/0934 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2004
From: SHIN, KANG SUP; RYU, SANG WOOK
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015525/0772 →