Interdigitaded capacitors
View Patent ↗The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.
1. Method for the manufacture of a capacitor pair device, the capacitor pair device having a first capacitor and a second capacitor, comprising the steps of:
a. providing a substrate,
b. depositing an electrically conductive layer on the substrate,
c. patterning the conductive layer in a single operation to form:
i. a first conductive comb structure forming a plate of the first capacitor of the capacitor pair,
ii. a second conductive comb structure forming another plate of the second capacitor of the capacitor pair, the second conductive comb structure interdigitated with the first comb structure, and
iii. a continuous conductive runner interleaved between the first conductive comb structure and the second conductive comb structure, the continuous conductive runner forming the first capacitor with the first conductive comb structure and the second capacitor with the second conductive comb structure, thus forming the capacitor pair.
2. The method of claim 1 including the step of forming an insulating layer on the capacitor pair, and repeating steps b. and c.
3. The method of claim 1 wherein step c. includes forming interconnections to one or more elements selected from the group consisting of resistors, inductors, transistors and diodes.
4. Method for the manufacture of a capacitor pair device, the capacitor pair device having a first capacitor and a second capacitor, comprising the steps of:
a. providing a substrate,
b. depositing an electrically conductive layer on the substrate,
c. patterning the conductive layer in a single operation to form:
i. a first conductive comb structure forming another plate of the first capacitor of the capacitor pair,
ii. a second conductive comb structure forming a plate of the second capacitor of the capacitor pair, the second conductive comb structure interdigitated with the first conductive comb structure,
iii. a first continuous conductive runner interleaved between the first conductive comb structure and the second conductive comb structure, the first continuous conductive runner forming the first capacitor with the first conductive comb structure,
iv. a second continuous conductive runner parallel to the first continuous conductive runner, and interleaved between the first continuous conductive runner and the second conductive comb structure, the second continuous conductive runner forming the second capacitor with the second conductive comb structure, thus forming the capacitor pair.
5. The method of claim 4 including the step of forming an insulating layer on the capacitor pair, and repeating steps b. and c.
6. The method of claim 4 wherein step c. includes forming interconnections to one or more elements selected from the group consisting of resistors, inductors, transistors and diodes.
7. The method of claim 4 wherein step c. additionally includes forming a ground plane between the first continuous runner and the second continuous runner.
8. A method of manufacturing an integrated circuit including a capacitor pair, the capacitor pair comprising a first capacitor and a second capacitor, comprising the steps of
a. providing a substrate,
b. depositing an electrically conductive layer on the substrate,
c. patterning the conductive layer in a single operation to form:
i. a first conductive comb structure forming a plate of the first capacitor of the capacitor pair,
ii. a second conductive comb structure forming another plate of the second capacitor of the capacitor pair, the second conductive comb structure interdigitated with the first conductive comb structure, and
iii. a continuous conductive runner interleaved between the first conductive comb structure and the second conductive comb structure, the continuous conductive runner forming the first capacitor with the first comb structure and the second capacitor with the second conductive comb structure, thus forming the capacitor pair.
9. The method of claim 8 including the step of forming an insulating layer on the capacitor pair, and repeating steps b. and c.
10. The method of claim 8 wherein step c. includes forming interconnections to one or more elements selected from the group consisting of resistors, inductors, transistors and diodes.