Digital control loop to improve phase noise performance and RX/TX linearity
View Patent ↗A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.
1. A system for controlling a voltage controlled oscillator (VCO), the VCO including a bias transistor and at least one output line, the system comprising:
an amplitude detector configured to detect an amplitude value at the at least one output line;
a comparator configured to compare the detected amplitude value with a predetermined amplitude value, and to output a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value;
an accumulator configured to accumulate outputs of the comparator so as to provide an accumulated digital amplitude value;
a digital-to-analog converter to convert the accumulated digital amplitude value to an accumulated analog amplitude value,
wherein the analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO.
2. The system according to claim 1 , wherein the at least one output line corresponds to two output lines of a differential VCO.
3. The system according to claim 1 , wherein the at least one output line corresponds to four output lines of a quadrature VCO.
4. The system according to claim 1 , wherein the at least one output line corresponds to one output line of a single-output VCO.
5. The system according to claim 1 , wherein the VCO further includes an LC circuit provided between the bias transistor and VCO switch transistors.
6. The system according to claim 1 , wherein the bias control signal corresponds to a bias voltage signal provided to a gate of the bias transistor.
7. The system according to claim 1 , wherein the bias control signal corresponds to a bias voltage provided to a gate of the bias transistor.
8. The system according to claim 1 , further comprising a control circuit configured to turn off the comparator, the amplitude detector, the accumulator and the digital-to-analog converter when the accumulated digital amplitude value has remained constant for at least a predetermined amount of time.
9. A system for controlling a voltage controlled oscillator (VCO), the VCO including a bias transistor, the system comprising:
a voltage detector configured to detect a voltage value at a node that is directly coupled to the bias transistor;
a comparator configured to compare the detected voltage value with a predetermined voltage value, and to output a first digital value when the detected voltage value is greater than the predetermined voltage value, and a second digital value when the detected voltage value is less than the predetermined voltage value;
an accumulator configured to accumulate outputs of the comparator so as to provide an accumulated digital voltage value;
a digital-to-analog converter to convert the accumulated digital voltage value to an accumulated analog voltage value,
wherein the accumulated analog voltage value is provided as an updated bias control signal to the bias transistor of the VCO.
10. The system according to claim 9 , wherein the node corresponds to a point between the bias transistor and an LC circuit of the VCO.
11. The system according to claim 9 , wherein the at least one output line corresponds to two output lines of a differential VCO.
12. The system according to claim 9 , further comprising a control circuit configured to turn off the comparator, the voltage detector, the accumulator and the digital-to-analog converter when the accumulated digital voltage value has remained constant for at least a predetermined amount of time.
13. A method for controlling a LO buffer, the LO buffer including a bias transistor and at least one output line, the method comprising:
detecting an amplitude value at a node corresponding to the at least one output line;
comparing the detected amplitude value with a predetermined amplitude value, and to output a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value;
accumulating outputs of the comparing step so as to provide an accumulated digital amplitude value; and
converting the accumulated digital amplitude value to an accumulated analog amplitude value,
wherein the analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the LO buffer.
14. The method according to claim 13 , wherein the node corresponds to a point between the bias transistor and a load of the LO buffer.
15. The method according to claim 13 , wherein the at least one output line corresponds to two output lines of a differential LO buffer.
16. The method according to claim 13 , wherein the at least one output line corresponds to four output lines of a quadrature LO buffer.
17. The method according to claim 13 , wherein the at least one output line corresponds to one output line of a single-output LO buffer.
18. The method according to claim 13 , further comprising:
providing the bias control signal to a gate of the bias transistor.
19. The method according to claim 13 , further comprising:
monitoring the accumulated digital amplitude value to determine if it has not changed for at least a first period of time; and
turning off a comparator, an amplitude detector, an accumulator and a digital-to-analog converter of a control feedback loop when the accumulated digital amplitude value has not changed for at least the first period of time.
20. A method for controlling a LO buffer, the LO buffer including a bias transistor, the method comprising:
detecting a voltage value at a node that is directly coupled to the bias transistor;
comparing the detected voltage value with a predetermined voltage value, and to output a first digital value when the detected voltage value is greater than the predetermined voltage value, and a second digital value when the detected voltage value is less than the predetermined voltage value;
accumulating outputs of the comparing step so as to provide an accumulated digital voltage value; and
converting the accumulated digital voltage value to an accumulated analog voltage value,
wherein the accumulated analog voltage value is provided as an updated bias control signal to the bias transistor of the LO buffer.
21. The method according to claim 20 , wherein the node corresponds to a point between the bias transistor and an LC circuit of the LO buffer.
22. The method according to claim 20 , wherein the at least one output line corresponds to two output lines of a differential LO buffer.
23. The method according to claim 20 , further comprising:
monitoring the accumulated digital voltage value to determine if it has not changed for at least a first period of time; and
turning off a comparator, a voltage detector, an accumulator and a digital-to-analog converter of a control feedback loop when the accumulated digital voltage value has not changed for at least the first period of time.