IP Library Granted Patent US 7,356,317
Granted Patent B2
US 7,356,317 · App. 10/890,712 · Granted Apr 8, 2008

Adaptive-biased mixer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,356,317
App. No.
10/890,712
Granted
Apr 8, 2008
Kind
B2
Abstract

A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.

Claims (48)

1. An adaptive biased mixer, comprising:

a circuit network that receives an RF differential signal pair and that outputs a differential signal pair;

a plurality of switching transistors that receive the differential signal pair output by the circuit network and that perform mixing with a differential local oscillation (LO) signal pair received on a LO input; and

an active bias circuit that performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and a differential output of the plurality of switching transistors;

wherein the plurality of switching transistors are biased, without supply of bias from a DC bias current source, to a same voltage via the active bias circuit; and

wherein the active bias circuit defines bias signals of the plurality of switching transistors via the feedback loop, which adaptively controls a LO bias voltage of each switching transistor.

2. The adaptive biased mixer according to claim 1 , further comprising:

a load network that is coupled to the differential output of the plurality of switching transistors, and that provides a load for the differential output of the plurality of switching transistors.

3. The adaptive biased mixer according to claim 2 , further comprising:

a DC offset cancellation circuit provided between the plurality of switching transistors and the active bias circuit.

4. The adaptive biased mixer according to claim 1 , further comprising:

a DC offset cancellation circuit provided between the plurality of switching transistors and the active bias circuit.

5. The adaptive biased mixer according to claim 1 , wherein at least one of the plurality of switching transistors is an N-type metal oxide semiconductor (NMOS) transistor.

6. The adaptive biased mixer according to claim 1 , wherein at least one of the plurality of switching transistors is a P-type metal oxide semiconductor (PMOS) transistor.

7. The adaptive biased mixer according to claim 1 wherein at least one of the plurality of switching transistors is a bipolar junction transistor (BJT).

8. The adaptive biased mixer according to claim 1 , wherein at least one of the plurality of switching transistors is a field effect transistor (FET).

9. adaptive biased mixer according to claim 1 , wherein the active bias circuit comprises an operational amplifier.

10. The adaptive biased mixer according to claim 1 , further comprising:

a low noise amplifier (LNA) that is folded with the mixer.

11. An adaptive biased mixer, comprising:

an input circuit that receives an RF signal;

switching circuitry that switches the RF signal with a local oscillation (LO) signal received on an LO input, to perform a mixing of the RF signal with the LO signal to provide a mixed signal; and

active bias circuitry that performs active biasing of the switching circuitry in a feedback loop provided between the LO input and an output of the switching circuitry;

wherein transistors in the switching circuitry are biased, without supply of bias from a DC bias current source, to a same voltage via the active bias circuit; and

wherein the active bias circuitry defines bias signals of the transistors via the feedback loop, which adaptively controls a LO bias voltage of each switching transistor.

12. The adaptive biased mixer according to claim 11 , wherein the received RF signal is a differential RF signal pair, and wherein the switching circuitry performs mixing with a differential local oscillation signal pair received on the LO input.

13. The adaptive biased mixer according to claim 12 , further comprising:

load circuitry that provides a load for the differential output of the switching means.

14. The adaptive biased mixer according to claim 11 , further comprising:

a DC offset cancellation that cancels a DC offset in signals output by the adaptive biased mixer.

15. The adaptive biased-mixer according to claim 11 , wherein the switching circuitry includes at least one metal oxide semiconductor (MOS) switching transistor.

16. The adaptive biased-mixer according to claim 11 , wherein the switching circuitry includes at least one bipolar junction (BJT) switching transistor.

17. The adaptive biased-mixer according to claim 11 , wherein the switching circuitry includes at least one field effect (FET) switching transistor.

18. The adaptive biased-mixer according to claim 11 , wherein the active bias circuitry includes an operational amplifier.

19. A method of providing a highly-linear output for a mixer, comprising:

receiving an RF signal output by a low noise amplifier;

switching the RF signal with a local oscillation (LO) signal received on an LO input, to perform a mixing of the RF signal with the LO signal to provide a mixed signal, the switching being perform by using a plurality of switching transistors;

performing active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the mixer, wherein the plurality of switching transistors are biased, without supply of bias from a DC bias current source, to a same voltage via the active bias circuit; and

defining bias signals of the plurality of switching transistors via the feedback loop, which adaptively controls a LO bias voltage of each switching transistor.

20. The method according to claim 19 , wherein the received RF signal is a differential RF signal pair, and wherein the switching step performs mixing with a differential local oscillation signal pair received on the LO input.

21. The method according to claim 19 , wherein at least one of the plurality of switching transistors is a metal oxide semiconductor (MOS) transistor.

22. The method according to claim 19 , wherein at least one of the plurality of switching transistors is a bipolar junction transistor (BJT).

23. The method according to claim 19 , wherein at least one of the plurality of switching transistors is a field effect transistor (FET).

24. The method according to claim 19 , wherein the active bias step includes feeding back a signal through an operational amplifier.

25. The method according to claim 19 , further comprising: canceling a DC offset in signals output by the mixer.

26. method according to claim 19 , further comprising: providing the mixed signal to a load network.

27. The method according to claim 19 , further comprising:

merging a low noise amplifier with the mixer, to provide a folder construction.

Assignments (14)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →