TDDB test pattern and method for testing TDDB of MOS capacitor dielectric
A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.
1. A unit test cell of a Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, comprising:
a MOS capacitor with a first electrode connected to ground;
a MOS transistor with a source electrode connected to the first electrode of the MOS capacitor and a drain electrode connected to a drain current measuring node (DCMN); and
a fuse with a first end connected to a voltage force node (VFN) and a second end connected to a second electrode of the MOS capacitor and the second end of the fuse also connected to a gate electrode of the MOS transistor, wherein both electrodes of the MOS capacitor are connected to electrodes of the MOS transistor.
2. The unit test cell of claim 1 , wherein the fuse is a metal line having a smaller width than a wiring line of the unit test cell.
3. The unit test cell of claim 1 , wherein a type of the MOS capacitor is the same as a type of the MOS transistor.
4. The unit cell of claim 3 , wherein both the type of the MOS capacitor and the type of the MOS transistor is NMOS.
5. The unit test cell of claim 1 , wherein a type of the MOS capacitor is different from a type of the MOS transistor.
6. The unit cell of claim 5 , wherein the type of the MOS capacitor is NMOS and the type of the MOS transistor is PMOS.
7. The unit cell of claim 1 , wherein a gate oxide film of the MOS transistor is thicker than a dielectric film of the MOS capacitor.
8. The unit cell of claim 1 , wherein the gate electrode of the MOS transistor is lightly doped such that a voltage applied to the gate electrode is less than the VFN voltage.
9. The unit cell of claim 1 , wherein the gate electrode of the MOS transistor is connected to the second electrode of the MOS capacitor.
10. The unit cell of claim 1 , wherein the second end of the fuse is directly connected to the gate electrode of the MOS transistor.
11. The unit test cell of claim 1 , wherein the first end of the fuse is connected to a stress voltage through the voltage force node so as to apply a stress voltage to said MOS capacitor and said MOS transistor.
12. The unit test cell of claim 1 , wherein the drain current measuring node is connected to an ammeter.
13. The unit test cell of claim 12 , wherein the ammeter is connected to a drain voltage source.