Semiconductor package with controlled solder bump wetting and fabrication method therefor
View Patent ↗A semiconductor package and a method of manufacturing a semiconductor package include a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
1. A method of manufacturing a semiconductor package, comprising:
providing a substrate having a plurality of lead fingers;
attaching a plurality of stud bumps to the plurality of lead fingers;
forming the plurality of stud bumps to form flat bondable surface thereon;
providing a die having a plurality solder bumps;
attaching the plurality of solder bumps to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps; and
encapsulating the die, the electrical connections, and the lead fingers to expose a lower surface of the plurality of lead fingers.
2. The method of manufacturing a semiconductor package as claimed in claim 1 , wherein:
providing the plurality of solder bumps provides a plurality of solder bumps having a first diameter; and
attaching the plurality of stud bumps attaches a plurality of stud bumps having a second diameter smaller than or substantially equal to the first diameter.
3. The method of manufacturing a semiconductor package as claimed in claim 1 , wherein attaching the plurality of stud bumps uses a wire bonding process.
4. The method of manufacturing a semiconductor package as claimed in claim 1 , wherein:
attaching a plurality of stud bumps attaches a plurality of clusters of stud bumps; and
the plurality of clusters of stud bumps comprise at least two stud bumps.
5. The method of manufacturing a semiconductor package as claimed in claim 1 , wherein attaching the plurality of stud bumps attaches stud bumps of at least one of copper, gold, and a combination thereof.
6. A method of manufacturing a semiconductor package, comprising:
providing a leadframe having a plurality of lead fingers;
attaching a plurality of stud bumps to the plurality of lead fingers;
forming the plurality of stud bumps to form flat bondable surfaces thereon;
providing a die having a plurality solder bumps;
vertically aligning the plurality of solder bumps to the plurality of stud bumps;
reflowing the plurality of solder bumps to form a plurality of electrical connections with the plurality of stud bumps and provide controlled collapse of the plurality of solder bumps; and encapsulating the die, the electrical connections, and the lead fingers to expose a lower surface of the plurality of lead fingers.
7. The method of manufacturing a semiconductor package as claimed in claim 6 , wherein:
providing the plurality of solder bumps provides a plurality of solder bumps having a first diameter; and
attaching the plurality of stud bumps attaches a plurality of stud bumps having a second diameter smaller than or substantially equal to the first diameter.
8. The method of manufacturing a semiconductor package as claimed in claim 6 , wherein attaching the plurality of stud bumps uses a wire bonding process.
9. The method of manufacturing a semiconductor package as claimed in claim 6 , wherein:
attaching a plurality of stud bumps attaches a plurality of clusters of stud bumps; and
the plurality of clusters of stud bumps comprise at least two stud bumps.
10. The method of manufacturing a semiconductor package as claimed in claim 6 , wherein attaching the plurality of stud bumps attaches stud bumps of at least one of copper, gold, and a combination thereof.