Clock tree network in a field programmable gate array
View Patent ↗A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.
1. A clock tree distribution network for a field programmable gate array (FPGA) comprising:
an interface having a root signal selected from at least one of an external clock signal, an internal clock signal and a plurality of phase lock loop cell output signals, said interface having programmable elements;
a logic array having a plurality of local signals and having programmable elements;
a programmable routing architecture coupled to said programmable elements of said interface and said logic array;
a routed clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to at least one of a plurality of logic modules and a plurality of flip-flops in said logic array; and
a hardwired clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to said plurality of flip-flops in said logic array.
2. The clock tree distribution network according to claim 1 further comprising:
a clock tile distribution cluster having a hardwired clock distribution module configured to receive said root signal for said hardwired clock network and a routed clock distribution module configured to receive said root signal for said routed clock network.
3. The clock tree distribution network according to claim 2 wherein said clock tile distribution cluster further comprises a plurality of routed clock modules, said modules comprising logic components programmed to select route one of a clock signal, a local signal, a positive power supply signal and a ground signal.
4. The clock tree distribution network according to claim 2 wherein said clock tile distribution cluster further comprises a plurality of hardwired clock modules, said hardwired clock modules comprising logic components programmed to select route one of a clock signal, a local signal, a positive power supply signal and a ground signal.
5. The clock tree distribution network according to claim 2 wherein said routed clock network comprises a plurality of routed clock clusters arranged in a column in said logic array and programmably coupled to said routed clock distribution module in said clock tile distribution cluster.
6. The clock tree distribution network according to claim 5 wherein said routed clock clusters further comprises a plurality of routed clock modules, said modules comprising logic components programmed to select and route one of a clock signal, a local signal from said routing architecture, a positive power supply signal and a ground signal.
7. The clock tree distribution network according to claim 2 wherein said hardwired clock network comprises a plurality of hardwired clock clusters arranged in a row in said logic array and programmably coupled to said hardwired clock distribution module in said clock tile distribution cluster.
8. The clock tree distribution network according to claim 7 wherein said hardwired clock clusters further comprises a plurality of hardwired clock modules, said hardwired clock modules comprising logic components programmed to select and route one of a clock signal, a local signal, a positive power supply signal and a ground signal.