Large-grain p-doped polysilicon films for use in thin film transistors
View Patent ↗A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.
1. A method for forming an array of thin film transistors, the method comprising:
depositing an amorphous semiconductor film by an LPCVD process wherein the film is in situ doped with a p-type dopant;
implanting hydrogen into the amorphous semiconductor film;
crystallizing the film; and
forming a plurality of thin film transistors, each thin film transistor comprising a channel region, each channel region comprising a portion of the crystallized film;
wherein the each of the plurality of thin film transistors comprises a charge storage region and the plurality of thin film transistors are SONOS-type memory cells.
2. The method of claim 1 wherein the crystallizing step comprises exposing the amorphous film comprising an amorphous silicon film to a crystallizing temperature about 540 degrees C. or greater.
3. The method of claim 2 wherein the crystallizing temperature is between about 540 and about 650 degrees C.
4. The method of claim 3 wherein the film is exposed to the crystallizing temperature for no more than about 24 hours.
5. The method of claim 4 wherein the film is exposed to the crystallizing temperature for no more than about twelve hours.
6. The method of claim 2 wherein the crystallizing temperature is between about 800 and about 900 degrees C.
7. The method of claim 6 wherein the film is exposed to the crystallizing temperature for between about 45 and about 60 seconds.
8. The method of claim 6 wherein the crystallizing step comprises thermally growing an oxide on the film.
9. The method of claim 1 wherein the film is doped to a dopant concentration between about 2×10 17 and about 2×10 18 atoms/cm 3 .
10. The method of claim 1 wherein the p-type dopant is boron.
11. The method of claim 1 wherein, during the crystallizing step, the film is not exposed to a catalytic metal.
12. The method of claim 1 wherein the depositing step is performed at a deposition temperature between about 460 and about 530 degrees C.
13. The method of claim 12 wherein the depositing step is performed at a deposition temperature between about 460 and about 520 degrees C.
14. The method of claim 1 wherein the crystallizing step does not include a laser annealing step.
15. The method of claim 1 wherein the crystallizing step comprises crystallizing substantially the entire film.
16. The method of claim 1 wherein the crystallizing step comprises crystallizing the film by solid phase crystallization.
17. A method for forming an array of thin film transistors, the method comprising:
depositing an amorphous silicon film by an LPCVD process wherein the film is in situ doped with a p-type dopant by using BCl 3 gas;
crystallizing the film wherein p-type dopant atoms are substantially the only catalyzing agent in contact with or incorporated in the film; and
forming a plurality of thin film transistors wherein a channel region of each transistor comprises a portion of the crystallized film;
wherein the each of the plurality of thin film transistors comprises a charge storage region and the plurality of thin film transistors are SONOS-type memory cells.
18. The method of claim 17 wherein the crystallizing step comprises exposing the amorphous film to a crystallizing temperature about 540 degrees C. or greater.
19. The method of claim 18 wherein the crystallizing temperature is between about 540 and about 650 degrees C.
20. The method of claim 19 wherein the film is exposed to the crystallizing temperature for no more than about 24 hours.
21. The method of claim 19 wherein the film is exposed to the crystallizing temperature for no more than about twelve hours.
22. The method of claim 18 wherein the crystallizing temperature is between about 800 and about 900 degrees C.
23. The method of claim 22 wherein the film is exposed to the crystallizing temperature for between about 45 and about 60 seconds.
24. The method of claim 23 wherein the crystallizing step comprises thermally growing an oxide on the film.
25. The method of claim 17 wherein the p-type dopant is boron.
26. The method of claim 17 wherein, during the crystallizing step, the film is not exposed to a catalytic metal.
27. The method of claim 17 wherein the depositing step is performed at a deposition temperature between about 460 and about 530 degrees C.
28. The method of claim 27 wherein the depositing step is performed at a deposition temperature between about 460 and about 520 degrees C.
29. The method of claim 17 wherein the crystallizing step does not include a laser annealing step.
30. The method of claim 17 wherein the crystallizing step comprises crystallizing substantially the entire film.
31. The method of claim 17 wherein the crystallizing step comprises crystallizing the film by solid phase crystallization.
32. The method of claim 17 wherein the film is doped to a dopant concentration between about 2×10 17 and about 2×10 18 atoms/cm 3 .
33. The method of claim 17 , further comprising implanting hydrogen into the amorphous silicon film.
34. A method for forming a monolithic three dimensional memory array of thin film transistors, the method comprising:
depositing a first amorphous silicon film by an LPCVD process wherein the first film is in situ doped with a p-type dopant;
crystallizing the first silicon film;
forming a first plurality of thin film transistors wherein each transistor comprises a channel region, the channel region of each first transistor formed in a portion of the first film; and
monolithically forming a second plurality of thin film transistors above the first plurality.
35. The method of claim 34 wherein the crystallizing step comprises exposing the amorphous film to a crystallizing temperature about 540 degrees C. or greater.
36. The method of claim 35 wherein the crystallizing temperature is between about 540 and about 650 degrees C.
37. The method of claim 36 wherein the film is exposed to the crystallizing temperature for no more than about 24 hours.
38. The method of claim 37 wherein the film is exposed to the crystallizing temperature for no more than about twelve hours.
39. The method of claim 35 wherein the crystallizing temperature is between about 800 and about 900 degrees C.
40. The method of claim 39 wherein the film is exposed to the crystallizing temperature for between about 45 and about 60 seconds.
41. The method of claim 39 wherein the crystallizing step comprises thermally growing an oxide on the film.
42. The method of claim 34 wherein the film is doped to a dopant concentration between about 2×10 17 and about 2×10 18 atoms/cm 3 .
43. The method of claim 34 wherein the p-type dopant is boron.
44. The method of claim 34 wherein, during the crystallizing step, the first film is not exposed to a catalytic metal.
45. The method of claim 34 wherein the depositing step is performed at a deposition temperature between about 460 and about 530 degrees C.
46. The method of claim 34 wherein the depositing step is performed at a deposition temperature between about 460 and about 520 degrees C.
47. The method of claim 34 wherein the crystallizing step does not include a laser annealing step.
48. The method of claim 34 wherein each of the first plurality of thin film transistors comprises a charge storage region.
49. The method of claim 48 wherein the first plurality of thin film transistors are SONOS-type memory cells.
50. The method of claim 34 wherein the crystallizing step comprises crystallizing substantially the entire film.
51. The method of claim 34 wherein the crystallizing step comprises crystallizing the film by solid phase crystallization.