System and method of controlling a three-dimensional memory
View Patent ↗A system and method of controlling a three dimensional memory is disclosed. In a particular embodiment, the system is implemented as an integrated circuit including a microcontroller having a control signal output, a three-dimensional monolithic non-volatile memory having a plurality of levels of memory cells above a silicon substrate and having an input responsive to the control signal output, a counter coupled to the microcontroller, and a program memory. The counter is to step through a series of time steps defining a program pulse time interval of a first program pulse to be applied to at least one selected memory cell within the three-dimensional monolithic non-volatile memory. The program memory is accessible to the microcontroller, and the program memory includes a sequence of program instructions corresponding to a memory operation with respect to the three-dimensional monolithic non-volatile memory.
1. An integrated circuit comprising:
a microcontroller having a control signal output;
a three-dimensional monolithic non-volatile memory having a plurality of levels of memory cells above a silicon substrate and having an input responsive to the control signal output;
a counter coupled to the microcontroller, the counter to step through a series of time steps defining a program pulse time interval of a first program pulse to be applied to at least one selected memory cell within the three-dimensional monolithic non-volatile memory; and
a program memory accessible to the microcontroller, the program memory including a sequence of program instructions corresponding to a memory operation with respect to the three-dimensional monolithic non-volatile memory.
2. The integrated circuit of claim 1 , wherein the counter steps through time steps of a second program pulse that is applied to the selected memory cell in connection with the memory operation.
3. The integrated circuit of claim 2 , wherein the first program pulse has a first program voltage and wherein the second program pulse has a second program voltage that is greater than the first program voltage, but less than a predetermined maximum program voltage.
4. The integrated circuit of claim 1 , further comprising a user interface module responsive to user commands and a clock generator responsive to the user interface module, the microcontroller having a clock input responsive to the clock generator.
5. The integrated circuit of claim 1 , wherein the three-dimensional non-volatile memory includes a plurality of levels of memory cells stacked on or above one another.
6. The integrated circuit of claim 5 , wherein each of the plurality of levels of memory cells are stacked on or above one side of a substrate.
7. The integrated circuit of claim 1 , wherein the memory operation comprises a memory program operation.
8. The integrated circuit of claim 7 , wherein the memory program operation comprises a first portion including providing the first program pulse and a second portion including providing a read-after-write function.
9. The integrated circuit of claim 1 , wherein the memory operation comprises a memory erase operation, and wherein the first program pulse is applied to a plurality of memory cells, and wherein the three-dimensional monolithic non-volatile memory includes vertically stacked memory cells.
10. The integrated circuit of claim 1 , wherein the three-dimensional memory includes SONOS transistors.
11. The integrated circuit of claim 1 , wherein the three-dimensional memory includes TFT transistors.
12. The integrated circuit of claim 1 , wherein the three-dimensional memory is a floating gaze-based read-write non-volatile memory.
13. The integrated circuit of claim 1 , wherein the three-dimensional memory is a vertically stacked non-volatile memory device and wherein at least one of the memory cells includes a diode.
14. The integrated circuit of claim 1 , wherein the program memory is a two-dimensional non-volatile memory.
15. The integrated circuit of claim 1 , wherein the sequence of program instructions comprises a built-in self test procedure.
16. The integrated circuit of claim 1 , further comprising a random access memory coupled to the microcontroller.
17. The integrated circuit of claim 16 , wherein the random access memory stores at least a portion of the sequence of program instructions.
18. The integrated circuit of claim 16 , wherein the random access memory stores a second sequence of program instructions and wherein the microcontroller executes the second sequence of program instructions from the random access memory to execute a second memory operation upon the three-dimensional memory.
19. The integrated circuit of claim 1 , wherein at least a portion of the sequence of program instructions are stored within an array within the three-dimensional memory instead of within the program memory.
20. The integrated circuit of claim 1 , wherein the program memory is a dedicated electrically erasable programmable read only memory (EEPROM) device on the same substrate as the three-dimensional monolithic non-volatile memory.
21. The integrated circuit of claim 1 , further comprising additional circuit logic and further comprising a user interface module responsive to commands provided by the additional circuit logic, the user interface module coupled to the microcontroller.
22. The integrated circuit of claim 1 , wherein the program memory is a read only memory (ROM).
23. An integrated circuit comprising:
a microcontroller having a control signal output;
a three dimensional non-volatile memory having an input responsive to the control signal output: and
a program memory accessible to the microcontroller, the program memory including a sequence of program instructions corresponding to a memory operation with respect to the three dimensional non-volatile memory, wherein at least a portion of the sequence of program instructions are stored within an array within the three dimensional memory instead of within the program memory.