TFT mask ROM and method for making same

1. A mask ROM array, comprising:

a first set of enabled transistors in which each transistor contains a charge storage region; and

a second set of partially or totally disabled transistors;

wherein the first set of transistors and the second set of transistors comprise TFTs.

2. The array of claim 1 , wherein each transistor of the second set of transistors contains a charge storage region.

3. The array of claim 1 , wherein the second set of TFTs comprises a set of totally disabled TFTs.

4. The array of claim 1 , wherein the second set of TFTs comprises a plurality of totally disabled TFTs and a plurality of partially disabled TFTs.

5. The array of claim 1 , wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively removed.

6. The array of claim 1 , wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially or totally inoperative.

7. The array of claim 1 , wherein:

the TFTs are selected from one or more of top gate co-planar TFTs, top gate staggered TFTs, bottom gate co-planar TFTs and bottom gate staggered TFTs; and

the charge storage region comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals located between a gate and a channel of a TFT.

8. The array of claim 7 , further comprising:

a first plurality of spaced apart conductors disposed at a first height above a substrate in a first direction; and

a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction, each rail stack including:

a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductors;

a conductive film; and

the charge storage region disposed between a second surface of the first semiconductor layer and the conductive film.

9. The array of claim 8 , wherein:

the first plurality of conductors comprise first rails, each comprising a polysilicon layer in contact with a metal or a metal silicide layer;

the first semiconductor layer comprises a polysilicon layer;

the conductive film comprises a polysilicon layer and a metal silicide layer; and

the TFTs are formed at intersections of adjacent first rails and the second rail stacks, such that the conductive film comprises a gate of the TFTs, portions of the first semiconductor layer comprise TFT channel regions and the polysilicon layers of the first rails comprise at least a portion of TFT source and drain regions.

10. A monolithic three dimensional TFT mask ROM array, comprising a plurality of device levels, wherein at least one device level of the plurality of device levels comprises the array of claim 1 .

11. The array of claim 1 , wherein the array comprises an array of CMOS TFTs each comprising the charge storage region.

12. The array of claim 11 , wherein the programmed array comprises a static random access memory cell and a logic cell.

13. The array of claim 12 , wherein the static random access memory array comprises:

the first set of enabled transistors comprising a set of enabled access and inverter TFTs;

the second set of partially or totally disabled transistors comprising a set of disabled isolation TFTs having at least a portion of a channel region removed;

and a third set of isolation TFTs having at least a portion of a channel region removed and at least a portion of the charge storage region removed such that a gate electrode contacts source or drain regions of the TFTs of the third set.

14. The array of claim 12 , wherein the logic cell comprises at least one antifuse link connecting a gate electrode and a source or a drain of a TFT.

15. The array of claim 1 , further comprising at least one antifuse link connecting a gate electrode and a source or a drain of a TFT.

16. The array of claim 1 , wherein at least one transistor of the second set of transistors is programmed by a mask ROM programming technique and at least one other transistor of the first set of transistors is programmed by hot carrier injection or Fowler-Nordheim tunneling.

17. The array of claim 1 , wherein the first set of enabled transistors comprises a set of EEPROM transistors.

18. The array of claim 1 , wherein each transistor of the first set of enabled transistors contains a charge storage region located between a gate and a channel.

19. A mask ROM array, comprising:

a first set of enabled transistors in which each transistor contains a charge storage region; and

a second set of partially or totally disabled transistors;

wherein at least one transistor of the second set of transistors is programmed by a mask ROM programming technique and at least one other transistor of the first set of transistors is programmed by hot carrier injection or Fowler-Nordheim tunneling.

20. The array of claim 19 , wherein the programmed array comprises a static random access memory cell and a logic cell.

21. The array of claim 20 , wherein the logic cell comprises at least one antifuse link connecting a gate electrode and a source or a drain of a transistor.

22. The array of claim 19 , wherein each transistor of the second set of transistors contains a charge storage region.

23. The array of claim 19 , wherein each transistor of the first set of transistors contains the charge storage region located between a gate and a channel.

24. The array of claim 23 , wherein each transistor of the second set of transistors contains a charge storage region.

25. The array of claim 23 , wherein the charge storage region comprises a dielectric isolated floating gate.

26. The array of claim 23 , wherein the charge storage region comprises an ONO dielectric film.

27. The array of claim 23 , wherein the charge storage region comprises an insulating layer containing conductive nanocrystals.

28. The array of claim 23 , wherein the first set of enabled transistors comprises a set of EEPROM transistors.