Digital processor with pulse width modulation module having dynamically adjustable phase offset capability, high speed operation and simultaneous update of multiple pulse width modulation duty cycle registers
View Patent ↗A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
1. An apparatus for generating a phase offset pulse width modulation (PWM) output, comprising:
a timer;
an offset register;
an adder having a first input coupled to the timer and a second input coupled to the offset register;
a period register;
a subtractor having a first input coupled to an output of the adder and a second input coupled to the period register;
a multiplexer having a first input coupled to an output of the subtractor, a second input coupled to the output of the adder, and a third input having logic for selecting either the first or second input for coupling to an output of the multiplexer, wherein if a subtraction result of the subtractor is negative or zero then coupling the first input to the output of the multiplexer, and if a subtraction result of the subtractor is positive then coupling the second input to the output of the multiplexer;
a duty cycle register;
a comparator having a first input coupled to the duty cycle register and a second input coupled to the output of the multiplexer, wherein the comparator output comprises the phase offset PWM output.
2. The apparatus according to claim 1 , further comprising a digital processor coupled to the timer, the offset register, the period register and the duty cycle register.
3. The apparatus according to claim 2 , wherein the digital processor is selected from the group consisting of a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC) and a programmable logic array (PLA).
4. A method for generating a phase offset pulse width modulation (PWM) output, said method comprising the steps of:
providing a time value;
providing an offset value;
summing the time and offset values to generate a sum of the time and offset values;
providing a period value;
subtracting the period value from the sum of the time and offset values to generate a resulting subtraction value;
determining whether the resulting subtraction value is negative, zero or positive;
providing a duty cycle value;
comparing the duty cycle value with the resulting subtraction value if the resulting subtraction value is negative or zero;
comparing the duty cycle value with the sum of the time and offset values if the resulting subtraction value is positive; and
generating the phase offset PWM output from either the step of comparing the duty cycle value with the resulting subtraction value or the step of comparing the duty cycle value with the sum of the time and offset values.