Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface
A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and subtraction, complex multiply accumulate (MULACC), and real domain dual multiply-accumulators (MACs). The SoC may be programmed entirely from a microprocessor programming interface, using calls from a DSP library to execute DSP functions. The cores may also be programmed separately. Capability for programming and simulating the entire SoC are provided by a separate programming environment. The SoC may have heterogeneous processing cores in which either processing core may act as master or slave, or both cores may operate simultaneously and independently.
1. A single chip architecture for a digital signal processor (DSP) capable of performing operations on floating-point data in a complex domain, said single chip architecture comprising:
a program memory coupled to a local sequencer having an instruction decoder, a condition generator, a status register, and a program counter, said program memory further coupled to a data/program bus multiplexer;
a very large instruction word (VLIW) DSP core coupled to said program memory, and to said local sequencer, said VLIW DSP core having a multiple address generation unit coupled to an address register file and a data register file, said data register file coupled to said multiple address generation unit, to said address register file, and to an operator block, said operator block coupled to said address register file, and to said multiple address generation unit, said operator block having a first operator block portion and a second operator block portion coupled to each other, each of said first and said second operator block portions having a first and a second floating point/integer multiplier, a floating point/integer complex adder, and a floating point/integer adder, said first and said second floating point/integer multipliers coupled to said floating point/integer complex adder, said floating point/integer adder coupled to said complex adder and to said data register file, said floating point/integer complex adder having a first adder portion and a second adder portion;
a direct memory access (DMA) controller coupled to said local sequencer and said data/program bus multiplexer;
a microprocessor interface coupled to a shared memory, said shared memory further coupled to a data memory; and
a data buffer coupled to said data/program bus multiplexer, to said data memory, to said VLIW DSP core, and to said shared memory, wherein said single chip architecture is formed on a single integrated circuit chip.
2. The architecture of claim 1 , wherein said data register file is comprised of a first data register portion and a second data register portion.
3. The architecture of claim 2 , wherein said first and second data register portions comprise respectively a real data portion and an imaginary data portion.
4. The architecture of claim 1 , wherein said shared memory is comprised of a first shared memory bank and a second shared memory bank, said first and second shared memory banks each organized as a dual port memory.
5. The architecture of claim 1 , wherein said data memory is comprised of a first data memory bank and a second data memory bank, said first and second data memory banks each organized as a dual port memory.
6. The architecture of claim 1 , wherein said data buffer is comprised of a first data buffer portion and a second data buffer portion, said first and second data buffer portions each organized as a dual port memory.
7. A single chip architecture for a digital signal processor (DSP) capable of performing operations on floating-point data in a complex domain, said single chip architecture comprising:
a program memory coupled to a local sequencer having an instruction decoder, a condition generator, a status register, and a program counter, said program memory further coupled to a data/program bus multiplexer;
a very large instruction word (VLIW) DSP core coupled to said program memory, and to said local sequencer, said VLIW DSP core having a multiple address generation unit coupled to an address register file and a data register file, said data register file coupled to said multiple address generation unit, to said address register file, and to an operator block, said operator block coupled to said address register file, and to said multiple address generation unit, said operator block having a first operator block portion and a second operator block portion coupled to each other, each of said first and said second operator block portions having a first and a second floating point/integer multiplier, a floating point/integer complex adder, and a floating point/integer adder, said first and said second floating point/integer multipliers coupled to said floating point/integer complex adder, said floating point/integer adder coupled to said complex adder and to said data register file, said floating point/integer complex adder having a first adder portion and a second adder portion;
a microprocessor interface coupled to a shared memory, said shared memory further coupled to a data memory;
a data buffer coupled to said data/program bus multiplexer, to said data memory, to said VLIW DSP core, and to said shared memory, wherein said single chip architecture is formed on a single integrated circuit chip;
wherein said data register file is comprised of a first data register portion and a second data register portion; and
wherein said first and second data register portions comprise respectively a real data portion and an imaginary data portion.
8. The architecture of claim 7 including a direct memory access (DMA) controller coupled to said local sequencer and said data/program bus multiplexer.
9. The architecture of claim 7 , wherein said shared memory is comprised of a first shared memory bank and a second shared memory bank, said first and second shared memory banks each organized as a dual port memory.
10. The architecture of claim 7 , wherein said data memory is comprised of a first data memory bank and a second data memory bank, said first and second data memory banks each organized as a dual port memory.
11. The architecture of claim 7 , wherein said data buffer is comprised of a first data buffer portion and a second data buffer portion, said first and second data buffer portions each organized as a dual port memory.