Electric circuit for decoding a two-phase asynchronous data signal and corresponding decoding method, device for controlling equipment
View Patent ↗This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding clock using a counter powered by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
1. An electronic circuit for decoding an asynchronous two-phase data signal, the circuit comprising:
a logic block configured to receive a data signal, to detect transitions in the received data signal, and to generate a decoding clock, wherein each detected transition has a direction;
a counter electrically coupled to the logic block, the counter fed by an internal clock, the counter configured to repeatedly increment until detection of a transition in the data signal, and to decrement down to zero when the transition in the data signal is detected; and
a first comparator configured to receive output from the counter, the output being first divided by two, wherein predetermined intervals for detecting a transition are controlled by the first comparator and by the counter;
wherein the decoding clock is generated based on contents of the counter.
2. The circuit according to claim 1 , wherein the decoding clock is generated by taking into account peaks of a waveform representing the contents of the counter.
3. The circuit according to claim 2 , wherein each of the peaks is used to mark a transition that transports the value of a bit of the data signal.
4. The circuit according to claim 3 , wherein the direction of each of the transitions is analysed to decode a value of a bit of the data signal.
5. The circuit according to claim 1 , further comprising at least one register configured to store the contents of the counter when the transition is detected in the data signal.
6. The circuit according to claim 1 , further comprising an initializer, the initializer configured to activate incrementation of the counter during a first falling front of the data signal, the counter being forced to zero activating.
7. The circuit according to claim 1 , further comprising windowing means configured to limit the detection of a transition on predetermined intervals.
8. The circuit according to claim 7 , wherein each of the predetermined intervals covers approximately 50% of a binary time and is centred on the transitions.
9. The circuit according to claim 1 , further comprising a detector configured to detect interruption of the data signal.
10. The circuit according to claim 9 , wherein the interruption detector includes a second comparator fed by the output from the register multiplied by two, and the second comparator further fed by the counter.
11. The circuit according to claim 1 , further comprising a parasite rejecter configured to reject parasites on the data signal.
12. The circuit according to claim 11 , wherein the rejecter includes a digital filter fed by the data signal and controlled by the internal clock.
13. The circuit according to claim 1 , wherein the internal clock has a frequency at least 16 times greater than the data signal rate.
14. The circuit according to claim 1 , wherein the data signal is encoded using Manchester encoding.
15. The circuit according to claim 1 , wherein the data signal is organised into successive frames, each frame beginning with a start bit.
16. The circuit according to claim 1 , wherein the circuit is configured to receive and decode a sequence comprising an undefined number of data.
17. A method for decoding a two-phase asynchronous data frame,
the method comprising:
generating a decoding clock based on a counter fed by an internal clock;
incrementing the counter repeatedly until detection of a transition in the data signal; and
decrementing the counter down to zero when the transition in the data signal is detected;
receiving output from the counter in a first comparator, the output being first divided by two, controlling predetermined intervals, for detecting a transition, by the first comparator and by the counter.
18. A control device of equipment,
the control device comprising:
an electronic circuit configured to decode a two-phase asynchronous data signal, the electronic circuit including:
a logic block configured to receive a data signal, to detect transitions in the received data signal, and to generate a decoding clock;
the counter configured to increment repeatedly until detection of a transition in the data signal, and to decrement down to zero when the transition in the data signal is detected; and
further comprising a first comparator configured to receive output from the counter, the output being first divided by two, wherein predetermined intervals for detecting a transition are controlled by the first comparator and by the counter.
19. The control device according to claim 18 , wherein the equipment is a lighting equipment.
20. An electronic circuit for decoding an asynchronous two-phase data signal, the circuit comprising:
a logic block configured to receive a data signal, to detect transitions in the received data signal, and to generate a decoding clock, wherein each detected transition has a direction;
a counter electrically coupled to the logic block, the counter fed by an internal clock, the counter configured to repeatedly increment until detection of a transition in the data signal, and to decrement down to zero when the transition in the data signal is detected;
windowing means configured to limit detection of a transition on predetermined intervals;
a first comparator configured to receive output from the counter, the output being first divided by two, the predetermined intervals being controlled by the first comparator and by the counter;
wherein the decoding clock is generated based on contents of the counter.