Process and electronic decoding circuit for a diphase asynchronous frame whose length is not known in advance, corresponding application, computer programme and storage means
View Patent ↗A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that L min ≦L≦L max =(L min +k), where k is a predetermined whole number greater than or equal to one.
1. Decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit, wherein said decoding process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that L min <L<L max =(L min +k), where k is a predetermined whole number greater than or equal to one, wherein the step for automatically detecting the length L comprises itself the followings steps:
a) detection of a possible transition in a portion of the signal carrying the row bit (L min +p) where p is a variable of a whole number type that is initialized at 1;
b) if a transition is detected, the row bit (L min +p) is considered as an information bit and:
b-1) if (L min +p)=L max , the frame is treated as an information bit frame (L min +p);
b-2) if (L min +p)<L max , return to step a) after first incrementing p by one to treat a portion of the signal carrying the following bit,
and in that the step for automatically detecting the length of the frame comprises moreover a first step for verifying the decision, made during step c-1), to treat the frame as an information bit frame (L min +p), the said second verification step consisting of verifying that the row bit (L min +(p+1)) is a stop bit.
2. Process of claim 1 , wherein it comprises moreover a step for the selection of an operating mode of the electronic circuit from at least two possible operating modes, depending on the length L detected.
3. Process of claim 2 , wherein the said at least two operating modes are a normal mode and a test mode.
4. Process of claim 3 , wherein the said selection step is such that: if the length L detected is equal to L min , the normal mode is selected; if the length L detected is equal to L max , the test mode is selected.
5. Process of claim 3 , wherein when the test mode is selected, the electronic circuit treats like a test frame at least one frame received after the frame whose length L has been detected.
6. Process of claim 1 , wherein the automatic detection step of the length L of the frame itself comprises the following successive steps:
c) if no transition is detected, the row bit (L min +p) is considered as a stop bit and the frame is treated as a information bit frame (L min +(p−1)), and in that said steps a and b of claim 1 are iterated successively.
7. Process of claim 6 , wherein the step a itself comprises a windowing step, limiting to a determined time window the detection of a possible transition in the portion of the signal carrying the row bit (L min +p).
8. Process of claim 7 , wherein the windowing step uses a counter powered by an internal clock of the said circuit, and that is incremented from zero to a determined maximum value, then decremented from the maximum value to zero, and in that the said determined time window is defined as a time interval during which the current value of the counter is greater than or equal to a predetermined threshold.
9. Process of claim 8 , wherein the said maximum determined value of the counter is a predetermined value dependent on an emission frequency and a data signal transfer rate.
10. Process of claim 8 , wherein the said maximum determined value of the counter is read from a register having first memorized the contents of the counter during the detection of a transition in the portion of the data signal carrying the row bit L min .
11. Process of claim 8 , wherein the said predetermined threshold is equal to half of the said maximum determined value of the counter,, such that the said time window covers approximately 50% of a binary time.
12. Process of claim 6 , the said frame comprising L information bits followed by a first and a second stop bit, wherein the automatic detection step of the length of the said frame comprises moreover a second step to verify the decision made during step c), to treat the frame as an information bit frame (L min +(p−1)), the said first verification step consisting of verifying that the row bit (L min +(p+1)) is a second stop bit.
13. Process of claim 6 , wherein L max =(L min +1) and in that the step for treating the row bit L max itself comprises the following successive steps:
a′) detection of a possible transition in a portion of the signal carrying the row bit L max ;
b′) if no transition is detected, the row bit L max is considered as a stop bit and the frame is treated as a information bit frame L min ;
c′) if a transition is detected, the row bit L max is considered as an information bit and the frame is treated as an information bit frame L max .
14. Process of claim 1 , wherein the said data signal is encoded using Manchester coding.
15. Computer program product, wherein it comprises program code instructions to run the steps of the process of claim 1 , when the said program is run on a computer.
16. Storage means, possibly totally or partially removable, that may be read by a computer, storing a set of instructions that may be carried out by the said computer to implement the process of claim 1 .
17. Electronic circuit for decoding a diphase asynchronous frame carried by a data signal and comprising L information bits followed by at least one stop bit, wherein said electronic circuit comprising means for automatically detecting the length L of the frame in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that: L min ≦L≦L max =(L min +k), where k is a predetermined whole number greater than or equal to one, and in that said means for automatically detecting the length L of the frame comprise:
means for detecting a possible transition in a portion of the signal carrying the row bit (L min +p) where p is a variable of a whole number type that is initialized at 1;
means for estimating the row bit (L min +p) as an information bit, said means for estimating being activating if a transition is detected;
means for treating the frame, said means for treating being activating if a transition is detected and enabling to come to at least one of the following decisions:
c-1) if (L min +p) =L max , treating the frame as an information bit frame (L min +p);
b-2) if (L min +p) <L max , activating again said means for detecting by having incrementing p by one to treat a portion of the signal carrying the following bit, and in that said means for automatically detecting the length L of the frame comprise moreover first means for verifying the decision c-1 for treating the frame as an information bit frame (L min +p), said means of verifying comprising second means for verifying that the row bit (L min +(p+1)) is a stop bit.
18. Electronic decoding circuit of claim 17 , wherein it comprises moreover means for selecting an operating mode for the electronic circuit from at least two possible operating modes, according to the length L detected.
19. Control device for at least one piece of equipment, wherein it comprises an electronic decoding circuit of claim 17 .
20. Control device of claim 19 , wherein the equipment controlled is lighting equipment.