Method for forming gate oxide layer in semiconductor device

1. A method for forming gate oxide layers of a semiconductor device, comprising steps of:

defining a first, a second, and a third device region by forming device isolation regions on a semiconductor substrate;

forming a sacrificing dielectric layer on the substrate;

removing the sacrificing dielectric layer on the first device region by selective etching;

forming a first gate oxide layer by oxidizing the first device region;

removing the sacrificing dielectric layer on the second and third device regions;

forming a second gate oxide layer on the second and third device regions by oxidizing the substrate;

removing the second gate oxide layer on the third device region;

forming a photoresist pattern exposing the third device region and covering the first and second device regions; and

forming a third gate oxide layer by oxidizing the third device region.

2. The method of claim 1 , wherein the first to third gate oxide layers have different thicknesses.

3. The method of claim 2 , wherein the first gate oxide layer is thicker than the second gate oxide layer, and the second gate oxide layer is thicker than the third gate oxide layer.

4. The method of claim 1 , wherein the step of forming a sacrificing dielectric layer includes forming a nitride layer by depositing silicon nitride.

5. The method of claim 4 , further comprising forming an oxide layer on the nitride layer by depositing silicon oxide.

6. The method of claim 4 , wherein the nitride layer is formed with a thickness less than or equal to 100 Å.

7. The method of claim 5 , wherein the oxide layer is formed with a thickness less than or equal to 150 Å.

8. The method of claim 4 , wherein the nitride layer is removed using a wet etching technique.

9. The method of claim 5 , wherein the oxide layer is removed using a dry etching technique.

10. A method for forming gate oxide layers of a semiconductor device, comprising steps of:

a step for defining a first, a second, and a third device region by forming device isolation regions on a semiconductor substrate;

a step for forming a sacrificing dielectric layer on the substrate;

a step for removing the sacrificing dielectric layer on the first device region by selective etching; a step for forming a first gate oxide layer by oxidizing the first device region;

a step for removing the sacrificing dielectric layer on the second and third device regions;

a step for forming a second gate oxide layer on the second and third device region by oxidizing the substrate;

a step of removing the second gate oxide layer on the third device region;

a step for forming a photoresist pattern exposing the third device region and covering the first and second device regions;

a step for forming a third gate oxide layer by oxidizing the third device region

a step of forming a polycrystalline silicon layer for a gate on the substrate; and

a step of selectively etching the polycrystalline silicon layer to form gates on the respective device region.

11. The method of claim 10 , wherein the first to third gate oxide layers have different thicknesses.

12. The method of claim 11 , wherein the first gate oxide layer is thicker than the second gate oxide layer, and the second gate oxide layer is thicker than the third gate oxide layer.

13. The method of claim 10 , wherein the step for forming a sacrificing dielectric layer includes a step for forming a nitride layer by depositing silicon nitride.

14. The method of claim 13 , further comprising a step for forming an oxide layer on the nitride layer by depositing silicon oxide.

15. The method of claim 13 , wherein the nitride layer is formed with a thickness less than or equal to 100 Å.

16. The method of claim 14 , wherein the oxide layer is formed with a thickness less than or equal to 150 Å.

17. The method of claim 13 , wherein the sacrificing nitride layer is removed using a wet etching technique.

18. The method of claim 14 , wherein the oxide layer is removed using a dry etching technique.