Method for forming dual damascene interconnection in semiconductor device
View Patent ↗A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating film. A sacrificial film is formed to fill the via hole. Portions of the intermetal insulating film and the sacrificial film are removed to form a trench. The sacrificial film is removed to expose the portion of the surface of the etch stop film. A plasma etching process is performed at a predetermined temperature using an etching gas to remove the exposed portion of the etch stop film and to prevent or suppress generation of a polymer. A diffusion barrier film is formed within the trench and the via hole such that the diffusion barrier contacts the lower metal film. An upper metal film is formed on the diffusion barrier.
1. A method for forming a dual damascene interconnection in a semiconductor device, comprising the steps of:
forming an etch stop film and an intermetal insulating film sequentially on a lower metal film;
forming a via hole to expose a portion of a surface of the etch stop film through the intermetal insulating film;
forming a sacrificial film with which the via hole is filled;
removing portions of the intermetal insulating film and the sacrificial film to form a trench;
removing the sacrificial film to expose the portion of the surface of the etch stop film;
performing a plasma etching process at a temperature of 0–40° C. using a CF 4 /CHF 3 /CH 3 gas and an Ar gas to remove the exposed portion of the etch stop film;
forming a diffusion barrier film within the trench and the via hole such that the diffusion barrier contacts the lower metal film; and
forming an upper metal film on the diffusion barrier.
2. The method according to claim 1 , wherein the etch stop film comprises a nitride film.
3. A method for forming a dual damascene interconnection in a semiconductor device, comprising:
step for forming an etch stop film and an intermetal insulating film sequentially on a lower metal film;
step for forming a via hole to expose a portion of a surface of the etch stop film through the intermetal insulating film;
step for forming a sacrificial film with which the via hole is filled;
step for removing portions of the intermetal insulating film and the sacrificial film to form a trench;
step for removing the sacrificial film to expose the portion of the surface of the etch stop film;
step for performing a plasma etching process at a temperature of 0–40 C. using a CF 4 /CHF 3 /CH 3 gas and an Ar gas to remove the exposed portion of the etch stop film;
step for forming a diffusion barrier film within the trench and the via hole such that the diffusion barrier contacts the lower metal film; and
step for forming an upper metal film on the diffusion barrier.
4. The method according to claim 3 , wherein the etch stop film comprises a nitride film.