IP Library Granted Patent US 7,339,251
Granted Patent B2
US 7,339,251 · App. 11/026,926 · Granted Mar 4, 2008

Shallow trench isolation structure and formation method thereof

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Quick Facts
Patent No.
US 7,339,251
App. No.
11/026,926
Granted
Mar 4, 2008
Kind
B2
Abstract

A method for fabricating an STI structure in a semiconductor device is disclosed. A disclosed method comprises: forming a pad oxide layer and a pad nitride layer on a substrate in sequence; patterning the pad oxide layer and the pad nitride layer to expose a predetermined part of the surface of the silicon substrate; forming a trench by etching the exposed part of the silicon substrate; depositing a nitride layer inside the trench and on the entire surface of the resulting structure; forming a thin thermal oxide layer along the interface between a silicon substrate and the thin nitride layer; and performing a wet cleaning process to make a predetermined angle in the upper part of the trench.

Claims (17)

1. An STI structure comprising:

a trench with a predetermined depth in a substrate;

a nitride layer inside the trench, the nitride layer having a substantially planar upper surface that is coplanar with an upper surface of the trench;

a thin thermal oxide layer along the interface between the silicon substrate and the nitride layer, the thin thermal oxide layer having a substantially planar upper surface that is coplanar with the upper surface of the nitride layer, and

an insulation layer filling the trench, the insulation layer exposing the upper surface of the thin thermal oxide layer and covering the entire upper surface of the nitride layer.

2. An STI structure as defined by claim 1 , wherein the trench has a depth between 6000 Å and 7000 Å.

3. An STI structure as defined by claim 1 , wherein the nitride layer has a thickness between 100 Å and 300 Å.

4. An STI structure as defined by claim 1 , wherein the insulation layer has an upper surface tat is higher than an uppermost surface of the nitride layer and an uppermost surface of the thin thermal oxide layer.

5. An STI structure as defined by claim 1 , wherein the insulation layer is only on the nitride layer.

6. An STI structure as defined by claim 1 , wherein the insulation layer comprises an O 3 -TEOS oxide layer.

7. An STI structure as defined by claim 1 , wherein a width of a top surface of the insulation layer is narrower than a width of the trench.

8. An STI structure as defined by claim 7 , wherein the trench has a dept between 6000 Å and 7000 Å.

9. An STI structure as defined by claim 7 , wherein the nitride layer has a thickness between 100 Å and 300 Å.

10. An STI structure as defined by claim 7 , wherein the insulation layer has an upper surface that is higher than an uppermost surface of the nitride layer and an uppermost surface of the thin thermal oxide layer.

11. An STI structure as defined by claim 7 , wherein the insulation layer is only on the nitride layer.

12. An STI structure as defined by claim 11 , wherein the insulation layer exposes the thin thermal oxide layer.

13. An STI structure as defined by claim 7 , wherein the insulation layer comprises an O 3 -TEOS oxide layer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded May 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017616/0966 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: LEE, SANG YONG
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016132/0926 →