Transistors of semiconductor devices and methods of fabricating the same
View Patent ↗Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.
1. A transistor comprising;
an inversion epitaxial layer on a silicon substrate;
a silicon epitaxial layer having a trench formed over the inversion epitaxial layer;
reverse spacers on sidewalls of the trench;
a gate electrode above the inversion epitaxial layer between the reverse spacers;
spacers on the sidewalls of the gate electrode;
pocket-well regions under opposite sides of the gate electrode;
LDD regions positioned adjacent respective ones of the pocket-well regions;
source and drain regions positioned adjacent the LDD regions, the source and drain regions having a larger thickness than the LDD regions; and
a silicide layer positioned on the gate electrode and the source and drain regions.
2. The transistor as defined by claim 1 , wherein the inversion epitaxial layer is used as an SSR epitaxial channel.
3. The transistor as defined by claim 1 , wherein a gate channel is located under the gate electrode, the gate channel having a length defined by a length of the inversion epitaxial layer exposed between the reverse spacers.
4. The transistor as defined by claim 1 , wherein the gate electrode has a width smaller than the trench and larger than a space between the reverse spacers.
5. The transistor as defined by claim 1 , wherein the silicon epitaxial layer is ion-implanted above the source and drain regions to function as elevated source and drain regions.