IP Library Granted Patent US 7,094,687
Granted Patent B1
US 7,094,687 · App. 11/071,903 · Granted Aug 22, 2006

Reduced dry etching lag

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Quick Facts
Patent No.
US 7,094,687
App. No.
11/071,903
Granted
Aug 22, 2006
Kind
B1
Abstract

A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes. The isolated via holes are etched into the dielectric layer at second etch conditions until the isolated via holes are properly formed, and the second photoresist layer is removed. Electrically conductive vias are formed within both the dense via holes and the isolated via holes, and the second electrically conductive layer is formed over the dielectric layer. Electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

Claims (52)

1. A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer, the method comprising the sequential steps of:

forming the first electrically conductive layer,

forming a dielectric layer over the first electrically conductive layer,

forming a first photoresist layer over the dielectric layer,

patterning the first photoresist layer with a first via hole pattern that includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes,

etching the dense via holes into the dielectric layer at first etch conditions until the dense via holes are properly formed,

removing the first photoresist layer,

forming a second photoresist layer over the dielectric layer,

patterning the second photoresist layer with a second via hole pattern that excludes dense via holes, and includes isolated via holes,

etching the isolated via holes into the dielectric layer at second etch conditions until the isolated via holes are properly formed, wherein the first etch conditions are different from the second etch conditions,

removing the second photoresist layer,

forming electrically conductive vias within both the dense via holes and the isolated via holes, and

forming the second electrically conductive layer over the dielectric layer, where electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

2. The method of claim 1 , wherein the dense via holes and the isolated via holes all have a diameter of no more than about two hundred nanometers.

3. The method of claim 1 , wherein the etch is a reactive ion etch.

4. The method of claim 1 , wherein the etch is a physical etch.

5. The method of claim 1 , wherein the etch is a wet etch.

6. A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer, the method comprising the sequential steps of:

forming the first electrically conductive layer,

forming a dielectric layer over the first electrically conductive layer,

forming a first photoresist layer over the dielectric layer,

patterning the first photoresist layer with a first via hole pattern that excludes via holes that are all disposed within a first distance one from another, called dense via holes, and includes via holes that are disposed at greater than the first distance one from another, called isolated via holes,

etching the isolated via holes into the dielectric layer at first etch conditions until the isolated via holes are properly formed,

removing the first photoresist layer,

forming a second photoresist layer over the dielectric layer,

patterning the second photoresist layer with a second via hole pattern that includes dense via holes, and excludes isolated via holes,

etching the dense via holes into the dielectric layer at second etch conditions until the dense via holes are properly formed, wherein the first etch conditions are different from the second etch conditions,

removing the second photoresist layer,

forming electrically conductive vias within both the dense via holes and the isolated via holes, and

forming the second electrically conductive layer over the dielectric layer, where electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

7. The method of claim 6 , wherein the dense via holes and the isolated via holes all have a diameter of no more than about two hundred nanometers.

8. The method of claim 6 , wherein the etch is a reactive ion etch.

9. The method of claim 6 , wherein the etch is a physical etch.

10. The method of claim 6 , wherein the etch is a wet etch.

11. A method of forming via holes in a layer, the method comprising the steps of:

forming a first photoresist layer over the layer,

patterning the first photoresist layer with a first via hole pattern that includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes,

etching the dense via holes into the layer at first etch conditions until the dense via holes are properly formed,

removing the first photoresist layer,

forming a second photoresist layer over the layer,

patterning the second photoresist layer with a second via hole pattern that excludes dense via holes, and includes isolated via holes,

etching the isolated via holes into the layer at second etch conditions until the isolated via holes are properly formed, wherein the first etch conditions are different from the second etch conditions, and

removing the second photoresist layer.

12. The method of claim 11 , wherein the dense via holes and the isolated via holes all have a diameter of no more than about two hundred nanometers.

13. The method of claim 11 , wherein the etch is a reactive ion etch.

14. The method of claim 11 , wherein the etch is a physical etch.

15. The method of claim 11 , wherein the etch is a wet etch.

16. The method of claim 11 , further comprising forming electrically conductive vias within both the dense via holes and the isolated via holes.

17. The method of claim 11 , further comprising:

forming a first electrically conductive layer immediately underlying the layer,

forming a second electrically conductive layer immediately overlying the layer, and

electrically connecting the first electrically conductive layer and the second electrically conductive layer with electrically conductive vias within both the dense via holes and the isolated via holes through the layer.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035058/0248 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2005
From: EDA, MASAICHI
To: LSI LOGIC CORPORATION
Reel/Frame 016348/0479 →