Aluminum oxide as liner or cover layer to spacers in memory device
View Patent ↗For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al 2 O 3 for example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.
1. A method for fabricating a memory device, comprising:
forming spacers to sides of word-line gates;
forming aluminum oxide as one of a liner layer or a cover layer to said spacers; and
forming charge storage regions under the word-line gates, wherein the aluminum oxide blocks hydrogen from reaching the charge storage regions,
and wherein the liner layer is disposed between the spacers and the charge storage regions,
and wherein the cover layer remains over a conductive material formed on the word-line gates.
2. The method of claim 1 , wherein the aluminum oxide has a chemical composition of Al 2 O 3 .
3. The method of claim 1 , wherein the aluminum oxide as a liner layer is formed on the sides of the word-line gates before the spacers are formed.
4. The method of claim 3 , further comprising:
forming source/drain bit-line junctions in a semiconductor substrate across the word-line gates;
forming the aluminum oxide also over the semiconductor substrate between the word-line gates; and
forming a metal silicide on the word-line gates with the aluminum oxide preventing formation of the metal silicide on the semiconductor substrate between the word-line gates.
5. The method of claim 1 , wherein the aluminum oxide as a cover layer is formed on the spacers after the spacers are formed.
6. The method of claim 5 , further comprising:
forming an oxide liner layer on the sides of the word-line gates before the spacers are formed.
7. The method of claim 1 , wherein the memory device is a SONOS (semiconductor oxide nitride oxide semiconductor) flash memory device.
8. The method of claim 7 , further comprising:
forming source/drain bit-line junctions in a semiconductor substrate across the word-line gates; and
forming an ONO (oxide nitride oxide) stack on the semiconductor substrate before formation of the word-line gates on the ONO stack.
9. The method of claim 1 , further comprising:
forming source/drain bit-line junctions in a semiconductor substrate across the word-line gates; and
forming the aluminum oxide also over the semiconductor substrate between the word-line gates;
wherein the aluminum oxide has negative charge carriers for reducing bit-line to bit-line leakage current.
10. The method of claim 1 , further comprising:
forming the aluminum oxide also over an active area in a periphery region of the memory device;
patterning an interlayer insulating layer over the aluminum oxide in a first etch process using the aluminum oxide as an etch stop layer; and
patterning the aluminum oxide in a second etch process to form an opening through the interlayer insulating layer and the aluminum oxide over the active area;
wherein the interlayer insulating layer and an isolation structure surrounding the active area have a same etch selectivity that is different from an etch selectivity of the aluminum oxide.
11. The method of claim 10 , wherein interlayer insulating layer and the isolation structure are comprised of silicon dioxide (SiO 2 ).
12. A memory device, comprising:
spacers formed to sides of word-line gates;
aluminum oxide formed as one of a liner layer or a cover layer to said spacers; and
charge storage regions formed under the word-line gates, wherein the aluminum oxide is disposed to block hydrogen from reaching the charge storage regions,
and wherein the liner layer is disposed between the spacers and the charge storage regions,
and wherein the cover layer remains over a conductive material formed on the word-line gates.
13. The memory device of claim 12 , wherein the aluminum oxide has a chemical composition of Al 2 O 3 .
14. The memory device of claim 12 , wherein the aluminum oxide as a liner layer is formed on the sides of the word-line gates under the spacers.
15. The memory device of claim 14 , further comprising:
source/drain bit-line junctions formed in a semiconductor substrate across the word-line gates;
wherein the aluminum oxide is also disposed over the semiconductor substrate between the word-line gates; and
a metal silicide formed on the word-line gates without formation of the metal silicide on the semiconductor substrate between the word-line gates.
16. The memory device of claim 12 , wherein the aluminum oxide as a cover layer is formed over the spacers.
17. The memory device of claim 16 , further comprising:
an oxide liner layer formed between the sides of the word-line gates and the spacers.
18. The memory device of claim 12 , wherein the memory device is a SONOS (semiconductor oxide nitride oxide semiconductor) flash memory device further comprising:
source/drain bit-line junctions formed in a semiconductor substrate across the word-line gates; and
an ONO (oxide nitride oxide) stack formed on the semiconductor substrate with the word-line gates formed on the ONO stack.
19. A memory device, comprising:
spacers formed to sides of word-line gates;
aluminum oxide formed as one of a liner layer or a cover layer to said spacers;
charge storage regions formed under the word-line gates, wherein the aluminum oxide is disposed to block hydrogen from reaching the charge storage regions; and
source/drain bit-line junctions formed in a semiconductor substrate across the word-line gates, wherein the aluminum oxide is formed also over the semiconductor substrate between the word-line gates, and wherein the aluminum oxide has negative charge carriers for reducing bit-line to bit-line leakage current.
20. The memory device of claim 12 , further comprising:
an active area in a periphery region of the memory device, wherein the aluminum oxide is also formed over the active area;
an interlayer insulating layer formed over the aluminum oxide; and
an opening formed through the interlayer insulating layer and the aluminum oxide over the active area;
wherein the interlayer insulating layer and an isolation structure surrounding the active area have a same etch selectivity that is different from an etch selectivity of the aluminum oxide.