Granted Patent B1

US 7,927,723 · App. 11/091,524 · Granted Apr 19, 2011

Abstract

Claims (36)

1. A memory device comprising:

a plurality of memory cells, each memory cell storing two bits of information;

an interlayer dielectric; and

a film stack formed over the interlayer dielectric, the film stack comprising:

a first layer of material having a high extinction coefficient, where the high extinction coefficient ranges from about 0.5 to about 0.9; and

a second layer of material having a low extinction coefficient, where the low extinction coefficient ranges from about 0 to about 0.2,

where the first layer comprises silicon rich oxide (SiRO) and where the second layer comprises silicon oxynitride (SiON).

2. The film stack of claim 1 , where the first layer has a thickness ranging from about 300 Å to about 2000 Å.

3. The film stack of claim 2 , where the second layer has a thickness ranging from about 100 Å to about 1000 Å.

4. The film stack of claim 1 , where the first layer has a thickness of about 1000 Å.

5. The film stack of claim 4 , where the second layer is formed on the first layer and has a thickness of about 400 Å.

6. The film stack of claim 1 , where the first and second layer prevent ultraviolet induced damage to the device.

7. A memory device, comprising:

a plurality of memory cells, each memory cell storing two bits of information;

an interlayer dielectric formed over the plurality of memory cells; and

a film stack formed over the interlayer dielectric, the film stack comprising:

a first layer having a high extinction coefficient formed on the interlayer dielectric, where the high extinction coefficient ranges from about 2.5 to about 4.0; and

a second layer having a low extinction coefficient formed on the first layer, where the low extinction coefficient ranges from about 0.55 to about 0.7,

where the first layer comprises silicon rich oxide (SiRO) and where the second layer comprises silicon oxynitride (SiON), and

where the first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.

8. The memory device of claim 7 , where the first layer has a thickness ranging from about 300 Å to about 2000 Å.

9. The memory device of claim 8 , where the second layer has a thickness ranging from about 100 Å to about 1000 Å.

10. The memory device of claim 7 , where the first layer has a thickness of about 1000 Å.

11. The memory device of claim 10 , where the second layer is formed on the first layer and has a thickness of about 400 Å.

12. A memory device, comprising:

a plurality of memory cells, each memory cell storing two bits of information;

an interlayer dielectric formed over the plurality of memory cells; and

a film stack formed over the interlayer dielectric, the film stack comprising:

a first layer having a high extinction coefficient formed on the interlayer dielectric, wherein the high extinction coefficient ranges from about 3.5 to about 4.0; and

a second layer having a low extinction coefficient formed on the first layer, where the low extinction coefficient ranges from about 0.6 to about 0.7,

where the first layer comprises silicon rich oxide (SiRO) and where the second layer comprises silicon oxynitride (SiON) and

where the first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.

13. The memory device of claim 12 , where the first layer has a thickness ranging from about 300 Å to about 2000 Å.

14. The memory device of claim 13 , where the second layer has a thickness ranging from about 100 Å to about 1000 Å.

15. The memory device of claim 12 , where the first layer has a thickness of about 1000 Å.

16. The memory device of claim 15 , where the second layer is formed on the first layer and has a thickness of about 400 Å.

Assignments (10)