Semiconductor devices and methods of manufacturing the same
View Patent ↗Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insulating layer on the substrate; and a gate on the gate insulating layer. The substrate also includes first spacers on opposite side walls of the gate. Each of the first spacers has a notch at a lower end adjacent the substrate. The example device also includes second spacers on side walls of respective ones of the first spacers; source/drain junction regions of a second conductivity type in the substrate on opposite sides of the gate and the second spacers; and LDD regions of the second conductivity type in the substrate at opposite sides of the gate and the first spacers. Each of the LDD regions has an end adjacent a respective one of the junction regions. The disclosed example device also includes pocket regions of the first conductivity type in the substrate at opposite sides of the gate. Each of the pocket regions has an end adjacent a respective one of the LDD regions, and each of the pocket regions has more depth under the gate than in other regions.
1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a gate insulating layer on the substrate;
a gate on the gate insulating layer;
first dual spacer patterns directly on opposite side walls of the gate, the first dual spacer patterns having a notch at a lower end adjacent the substrate, wherein the notch has a size less than the thickness of the first dual spacer patterns;
second spacers on outer side walls of respective ones of the first dual spacer patterns;
source/drain junction regions of a second conductivity type in the substrate on opposite sides of the gate and the second spacers;
LDD regions of the second conductivity type in the substrate at opposite sides of the gate and the first dual spacer patterns, each of the LDD regions having an end adjacent a respective one of the junction regions; and
pocket regions of the first conductivity type in the substrate at opposite sides of the gate, each of the pocket regions having an end adjacent a respective one of the LDD regions, and each of the pocket regions having more depth under the gate than in other regions.
2. A semiconductor device as defined in claim 1 , wherein at least one of the first dual spacer patterns comprises:
an interior spacer pattern formed on the side wall of the gate; and
an exterior spacer pattern formed on a side wall of the interior spacer pattern.
3. A semiconductor device as defined in claim 2 , wherein:
the interior spacer pattern is an oxide layer; and
the exterior spacer pattern is a nitride layer.
4. A semiconductor device as defined in claim 1 , wherein the notch has a size of about 10 nm.