Non-volatile programmable memory cell and array for programmable logic array
View Patent ↗A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
1. A non-volatile programmable memory cell formed in a semiconductor substrate of a first conductivity type and comprising:
a non-volatile MOS transistor of a second conductivity type formed in a first semiconductor region of the first conductivity type and coupled between a first power supply potential and an output node;
a volatile MOS transistor of the first conductivity type formed in a semiconductor region of the second conductivity type and coupled between the output node and a second power supply potential; and
a volatile MOS switch transistor of the second conductivity type formed in a second semiconductor region of the first conductivity type and coupled to the output node;
wherein the first and second semiconductor regions of the first conductivity type are electrically isolated from one another.
2. The non-volatile programmable memory cell of claim 1 wherein said first semiconductor region of the first conductivity type is a well region of the first conductivity type formed within a first well region of the second conductivity type and the second semiconductor region of the first conductivity type is the semiconductor substrate.
3. The non-volatile programmable memory cell of claim 2 wherein the volatile MOS transistor of the first conductivity type is formed in the first well region of the second conductivity type.
4. The non-volatile programmable memory cell of claim 1 wherein said first semiconductor region of the first conductivity type is a first well region of the first conductivity type formed within a well region of the second conductivity type and the second semiconductor region of the first conductivity type is a second well region of the first conductivity type isolated from the first well region of the first conductivity type.
5. The non-volatile programmable memory cell of claim 4 wherein the volatile MOS transistor of the first conductivity type is formed in the first well region of the second conductivity type.
6. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a floating gate transistor.
7. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a flash transistor.
8. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a floating charge-trapping transistor.
9. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a nano-crystal transistor.
10. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is N and said second conductivity type is P.
11. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is P and said second conductivity type is N.
12. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is N, and said second conductivity type is P.
13. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is P, said second conductivity type is N.
14. The non-volatile programmable memory cell of claim 1 further including at least one additional volatile MOS switch transistor of the second conductivity type formed in the second semiconductor region of the first conductivity type and coupled to the output node.
15. A non-volatile programmable memory cell formed in a p-type semiconductor substrate and comprising:
a non-volatile n-channel MOS transistor formed in a first p-type semiconductor region and coupled between a first power supply potential and an output node;
a volatile p-channel MOS transistor formed in an n-type semiconductor region and coupled between the output node and a second power supply potential; and
a volatile n-channel MOS switch transistor formed in a second p-type semiconductor region and coupled to the output node;
wherein the first and second p-type semiconductor regions are electrically isolated from one another.
16. The non-volatile programmable memory cell of claim 15 wherein:
the n-type semiconductor region is an n-well disposed in the semiconductor substrate;
the first p-type region is a p-well disposed within the n-well; and
the second p-type semiconductor region is the substrate.
17. The non-volatile programmable memory cell of claim 15 wherein:
the n-type semiconductor region is an n-well disposed in the semiconductor substrate;
the first p-type region is a first p-well disposed within the n-well; and
the second p-type semiconductor region is a second p-well disposed in the substrate and isolated from the first p-well.
18. The non-volatile programmable memory cell of claim 15 further including at least one additional volatile n-channel MOS switch transistor formed in the second p-type semiconductor region and coupled to the output node.