Semiconductor devices and methods of manufacturing the same
View Patent ↗Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H 2 in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H 2 in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO 2 :H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N 2 annealing or Ar annealing.
1. A method for manufacturing a semiconductor device comprising:
forming a gate electrode on a semiconductor substrate, the gate electrode comprising a patterned polysilicon layer and having a side wall spacer on a sidewall thereof;
forming source and drain regions in the semiconductor substrate using the gate electrode and the side wall spacer as a mask;
forming a PMD liner layer on the gate electrode by sequentially forming a first SiO 2 :H layer, a SiON:H layer having a thickness of 50 Å to 200 Å using a plasma of SiH 4 , N 2 O, NH 3 , and He, and a SiN:H layer using a same deposition apparatus as the first SiO 2 :H layer and the SiON:H layer, wherein the PMD liner layer directly contacts the gate electrode and the source and drain regions;
forming an interlayer insulating layer above the PMD liner layer by an HDP method employing a plasma of SiH 4 , H 2 , and at least one of N, P, As, and a hydride of Sb or Bi; and
removing dangling bonds in the source and drain regions by diffusing hydrogen in the PMD liner layer and the insulating layer to the source and drain regions by N 2 annealing or Ar annealing.
2. A method as defined in claim 1 , wherein the first SiO 2 :H layer is formed using a plasma of SiH 4 , O 2 , H 2 , and He.
3. A method as defined in claim 1 , wherein the SiN:H layer is formed using a plasma of SiH 4 , NH 3 , and Ar.
4. A method as defined in claim 1 , wherein the first SiO 2 :H layer and the SiN:H layer have a thickness of 100 Å to 200 Å.
5. A method as defined in claim 1 , wherein the PMD liner layer has a thickness of 200 Å to 500 Å.
6. A method as defined in claim 4 , wherein the PMD liner layer has a thickness of 200 Å to 500 Å.
7. A method as defined in claim 1 , further comprising forming a protective layer before N 2 annealing or Ar annealing.
8. A method as defined in claim 1 , further comprising forming a protective layer after N 2 annealing or Ar annealing.
9. A method as defined in claim 1 , wherein the insulating layer comprises a second SiO 2 :H layer.
10. A method as defined in claim 4 , wherein the insulating layer comprises a second SiO 2 :H layer.
11. A method as defined in claim 5 , wherein the insulating layer comprises a second SiO 2 :H layer.
12. A method as defined in claim 9 , wherein the second SiO 2 :H layer comprises at least one of N, P, As or Sb.
13. A method as defined in claim 10 , wherein the second SiO 2 :H layer comprises at least one of N, P, As or Sb.
14. A method as defined in claim 11 , wherein the second SiO 2 :H layer comprises at least one of N, P, As or Sb.