Dual port gain cell with side and top gated read transistor
View Patent ↗A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
1. A memory cell comprising:
a first transistor having a gate, a first source, and a first drain;
a second transistor having a first gate, a second gate, a second source, and a second drain;
a trench located in a semiconductor-on-insulator (SOI) substrate including a stack of, from top to bottom, a semiconductor-on-insulator (SOI) layer, a buried insulator layer, and a bottom substrate layer; and
a capacitor having a first terminal and a storage node dielectric, wherein said first terminal of said capacitor and said second gate of said second transistor comprise a single entity and located in said trench, and wherein said storage node dielectric laterally abuts said SOI layer, said buried insulator layer, and said bottom substrate layer at sidewalls of said trench.
2. The memory cell of claim 1 wherein said first transistor is coupled to a write wordline of a memory array, a first node, and a bitline of said memory array; said second transistor is coupled to a read wordline, to said first node, to a voltage source and said bitline; and said capacitor is connected to said first node and further including a second terminal connected to a voltage source.
3. The memory cell of claim 2 wherein said second transistor contains a first surface and a second surface, wherein the first surface of said second transistor is horizontally oriented, and the second surface of said second transistor is vertically oriented.
4. The memory cell of claim 3 wherein a proximal end of said first surface is adjacent to a proximal end of said second surface, and a distal end of said first surface is adjacent to a distal end of said second surface.
5. The memory cell of claim 2 wherein the source of said second transistor is located on one of a proximal end or a distal end, and the drain of said second transistor is located on the other of the proximal end or the distal end.
6. The memory cell of claim 2 wherein the first gate of said second transistor is disposed on said first surface, and the second gate of said second transistor is disposed on said second surface.
7. The memory cell of claim 2 wherein said single entity is a capacitor electrode.
8. The memory cell of claim 1 wherein said first transistor is coupled to a write wordline of a memory array, a first node, and a write bitline of said memory array; said second transistor is coupled to a read wordline, to said first node, to a voltage source and a read bitline; and the first terminal of said capacitor is connected to said first node and said capacitor further includes a second terminal connected to a voltage source.
9. The memory cell of claim 8 wherein said second transistor contains a first surface and a second surface, wherein the first surface of said second transistor is horizontally oriented, and the second surface of said second transistor is vertically oriented.
10. The memory cell of claim 9 wherein a proximal end of said first surface is adjacent to a proximal end of said second surface, and a distal end of said first surface is adjacent to a distal end of said second surface.
11. The memory cell of claim 8 wherein the source of said second transistor is located on one of a proximal end or a distal end, and the drain of said second transistor is located on the other of the proximal end or the distal end.
12. The memory cell of claim 9 wherein the first gate of said second transistor is disposed on said first surface, and the second gate of said second transistor is disposed on said second surface.
13. The memory cell of claim 8 wherein said single entity is a capacitor electrode.
14. A memory cell comprising:
a first transistor having a gate, a first source, and a first drain;
a second transistor having a top gate, a side gate, a second source, and a second drain;
a trench located in a semiconductor-on-insulator (SOI) substrate including a stack of, from top to bottom, a semiconductor-on-insulator (SOI) layer, a buried insulator layer, and a bottom substrate layer; and
a capacitor having a first terminal and a storage node dielectric, wherein the first terminal of said capacitor and said side gate of said second transistor comprise a single entity and located in said trench, and wherein said storage node dielectric laterally abuts said SOI layer, said buried insulator layer, and said bottom substrate layer at sidewalls of said trench.
15. The memory cell of claim 1 wherein said second source and said second drain are located above an entirety of said buried insulator layer.
16. The memory cell of claim 1 wherein a portion of said storage node dielectric is located in said bottom substrate layer.
17. The memory cell of claim 14 wherein said second source and said second drain are located above an entirety of said buried insulator layer.
18. The memory cell of claim 14 wherein a portion of said storage node dielectric is located in said bottom substrate layer.
19. The memory cell of claim 1 wherein said trench extends from a top surface of said SOI layer, though an entirety of said buried insulator layer, and into said bottom substrate layer.
20. The memory cell of claim 14 wherein said trench extends from a top surface of said SOI layer, through an entirety of said buried insulator layer, and into said bottom substrate layer.