Microcontroller
View Patent ↗A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.
1. A microcontroller that receives and processes a demodulation signal generated by a receiver circuit on a receiving part of a wireless system, comprising:
a memory that stores a control program of said microcontroller, said control program including a dual loop routine for an operation in reception standby mode, and said dual loop routine having a first loop and a second loop included in said first loop; and
a CPU which has an instruction set consisting of a plurality of instructions and operates according to the control program stored in said memory, wherein
said CPU keeps a repetition cycle of said second loop a desired length by executing an instruction irrelevant to an operation of said microcontroller in reception mode a fixed number of times in said second loop in each execution of said second loop, the repetition cycle of said second loop being time required from beginning to end of an execution of said second loop, and
the fixed number of times is set to be greater than or equal to a number of times a peak value of a noise being lowered below a desired level and to less than or equal to a number of times the peak value of the noise being saturated, based on a characteristic in which the peak value of the noise generated in harmonics, whose frequency is an integral multiple of a repetition frequency of said second loop, becomes lower as the repetition cycle of said second loop increases due to increasing in the fixed number of times, and saturates at a background level.
2. The microcontroller according to claim 1 , wherein
said plurality of instructions includes an NOP instruction, and said instruction irrelevant to said operation of said microcontroller in reception mode is said NOP instruction.
3. The microcontroller according to claim 1 , wherein:
said plurality of instructions includes a first dummy instruction which requires a larger number of cycles for execution than other instructions, and said instruction irrelevant to said operation of said microcontroller in reception mode is said first dummy instruction.
4. The microcontroller according to claim 1 , wherein
said memory and said CPU are mounted in a same package together with said receiver circuit.